https://scholars.lib.ntu.edu.tw/handle/123456789/502240| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Huang, Y.-L. | en_US |
| dc.contributor.author | Liu, C.-S. | en_US |
| dc.contributor.author | Li, Y.-C. | en_US |
| dc.contributor.author | Lu, Y.-C. | en_US |
| dc.contributor.author | YI-CHANG LU | zz |
| dc.creator | YI-CHANG LU;Lu, Y.-C.;Li, Y.-C.;Liu, C.-S.;Huang, Y.-L. | - |
| dc.date.accessioned | 2020-06-16T06:36:19Z | - |
| dc.date.available | 2020-06-16T06:36:19Z | - |
| dc.date.issued | 2013 | - |
| dc.identifier.uri | https://scholars.lib.ntu.edu.tw/handle/123456789/502240 | - |
| dc.relation.ispartof | International System on Chip Conference | - |
| dc.title | Architecture and circuit design of parallel processing elements for de novo sequence assembly | en_US |
| dc.type | conference paper | - |
| dc.identifier.doi | 10.1109/SOCC.2013.6749659 | - |
| dc.identifier.scopus | 2-s2.0-84898464973 | - |
| dc.identifier.url | https://www.scopus.com/inward/record.uri?eid=2-s2.0-84898464973&doi=10.1109%2fSOCC.2013.6749659&partnerID=40&md5=4915f92e9e9cebe00b20f02bed59bd73 | - |
| dc.relation.pages | 50-54 | - |
| item.cerifentitytype | Publications | - |
| item.grantfulltext | none | - |
| item.fulltext | no fulltext | - |
| item.openairecristype | http://purl.org/coar/resource_type/c_5794 | - |
| item.openairetype | conference paper | - |
| crisitem.author.dept | Electronics Engineering | - |
| crisitem.author.dept | Electrical Engineering | - |
| crisitem.author.orcid | 0000-0002-7638-0367 | - |
| crisitem.author.parentorg | College of Electrical Engineering and Computer Science | - |
| crisitem.author.parentorg | College of Electrical Engineering and Computer Science | - |
| Appears in Collections: | 電機工程學系 | |
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