Architecture and circuit design of parallel processing elements for de novo sequence assembly

Journal

International System on Chip Conference

Pages

50-54

Date Issued

2013

Author(s)

Huang, Y.-L.

Liu, C.-S.

Li, Y.-C.

DOI

10.1109/SOCC.2013.6749659

URI

https://scholars.lib.ntu.edu.tw/handle/123456789/502240

URL

https://www.scopus.com/inward/record.uri?eid=2-s2.0-84898464973&doi=10.1109%2fSOCC.2013.6749659&partnerID=40&md5=4915f92e9e9cebe00b20f02bed59bd73

Type

conference paper