https://scholars.lib.ntu.edu.tw/handle/123456789/502382
標題: | A Static RAM Chip with On-Chip Error Correction | 作者: | Goodman, R.M. Sayano, M. TZI-DAR CHIUEH |
公開日期: | 1990 | 卷: | 25 | 期: | 5 | 起(迄)頁: | 1290-1294 | 來源出版物: | IEEE Journal of Solid-State Circuits | 摘要: | This paper describes a 2-kb CMOS static RAM with on-chip error-correction capability (ECCRAM chip). The chip employs the linear sum code (LSC) technique to perform error detection and correction. The ECCRAM chip has been fabricated in a double-metal scalable CMOS process with 3-μm feature size. Testing results of the actual chip shows a significant improvement in random error tolerance. © 1990 IEEE |
URI: | https://scholars.lib.ntu.edu.tw/handle/123456789/502382 | ISSN: | 00189200 | DOI: | 10.1109/4.62154 | SDG/關鍵字: | Codes, Symbolic - Error Correction; Data Storage, Digital - Random Access; Integrated Circuits, CMOS; Semiconductor Devices, MOS - Applications; CMOS Technology; Static Random-Access Memory (SRAM); Data Storage, Semiconductor |
顯示於: | 電機工程學系 |
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