|Title:||A flip-chip-assembled W-band receiver in 90-nm CMOS and IPD technologies||Authors:||CHUN-HSING LI
Hsieh, Wan Ting
Chiu, Te Yen
|Keywords:||CMOS | flip-chip assembly | frequency doubler (FD) | integrated-passive-device (IPD) | interconnect | low-noise amplifier (LNA) | mixer | receiver | variable-gain amplifier (VGA) | W-band||Issue Date:||1-Apr-2019||Publisher:||IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC||Journal Volume:||67||Journal Issue:||4||Start page/Pages:||1628||Source:||IEEE Transactions on Microwave Theory and Techniques||Abstract:||
© 2019 IEEE. A flip-chip-assembled W-band receiver composed of a 90-nm CMOS chip and an integrated-passive-device (IPD) carrier is presented in this paper. The chip which integrates a low-noise amplifier, a single-sideband mixer, a frequency doubler (FD), and a wide-band variable-gain amplifier, is flip-chip packaged to the IPD carrier through a low-loss interconnect. The simulated loss of the interconnect without any compensation network is only 0.95 dB at 94 GHz. The FD can provide differential output without any additional lossy balun required, effectively increasing the FD output power, and hence relaxing the local oscillator generation circuit design. The experimental results show that the proposed packaged receiver can provide a variable gain from 11.3 to 48.2 dB, while having an input 1-dB compression point from-43.7 to-29 dBm as the RF frequency is 90 GHz. The intermediate bandwidth and minimum noise figure can be 1.0 GHz and 7.8 dB, respectively. The proposed receiver only consumes 73.9 mW from a 1.2-V supply. As compared with prior works, the proposed receiver exhibits higher gain, lower noise, and lower power dissipation even though a less-advanced 90-nm CMOS technology is adopted. To the best of the authors' knowledge, this is the first W-band CMOS receiver assembled on an IPD carrier reported thus far.
|Appears in Collections:||電機工程學系|
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