https://scholars.lib.ntu.edu.tw/handle/123456789/516596
標題: | Single-trap-induced random telegraph noise for FinFET, Si/Ge Nanowire FET, Tunnel FET, SRAM and logic circuits | 作者: | M.-L. Fan S.-Y. Yang Y.-N. Chen P. Su C.-T. Chuang VITA PI-HO HU |
公開日期: | 2014 | 卷: | 54 | 期: | 4 | 起(迄)頁: | 698-711 | 來源出版物: | Microelectronics Reliability | 摘要: | In this paper, we comprehensively review the impacts of single-trap-induced random telegraph noise (RTN) on FinFET, Ge/Si Nanowire FET and Tunnel FET (TFET). The resulting influences on the thermionic-based current conduction such as FinFET, Si-NW FET and Ge-NW FET (at low drain bias) as well as interband tunneling dominated current conduction such as TFET and high-drain-biased Ge-NW FET are extensively addressed in device and circuit level. The location of the trap is shown to have profound impacts and the impacts vary with bias conditions and trap types. The worst-case analysis of the stability/performance and leakage/delay for all possible trapping/detrapping RTN combinations are investigated for FinFET, Si-/Ge-NW FETs and TFET based 6T/8T SRAM cells and logic circuits. © 2014 Elsevier Ltd. All rights reserved. |
URI: | https://scholars.lib.ntu.edu.tw/handle/123456789/516596 https://www.scopus.com/inward/record.uri?eid=2-s2.0-84897509265&doi=10.1016%2fj.microrel.2013.12.026&partnerID=40&md5=d82de00d2eb603f64951e30034ed8f92 |
ISSN: | 00262714 | DOI: | 10.1016/j.microrel.2013.12.026 | SDG/關鍵字: | Drain current; Germanium; Integrated circuits; Logic circuits; Silicon; Static random access storage; Bias conditions; Circuit levels; Current conduction; Interband tunneling; Random telegraph noise; Trapping/detrapping; Tunnel FET (TFET); Worst-case analysis; Field effect transistors |
顯示於: | 電機工程學系 |
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