https://scholars.lib.ntu.edu.tw/handle/123456789/559050
標題: | Learning to Automate the Design Updates from Observed Engineering Changes in the Chip Development Cycle | 作者: | Kravets, V.N. Jiang, J.-H.R. Riener, H. JIE-HONG JIANG |
公開日期: | 2020 | 起(迄)頁: | 738-743 | 來源出版物: | Proceedings of the 2020 Design, Automation and Test in Europe Conference and Exhibition, DATE 2020 | URI: | https://www.scopus.com/inward/record.url?eid=2-s2.0-85087387819&partnerID=40&md5=766046202dcbecc07c9110600ea6a3a4 https://scholars.lib.ntu.edu.tw/handle/123456789/559050 |
DOI: | 10.23919/DATE48585.2020.9116310 |
顯示於: | 電機工程學系 |
在 IR 系統中的文件,除了特別指名其著作權條款之外,均受到著作權保護,並且保留所有的權利。