https://scholars.lib.ntu.edu.tw/handle/123456789/559061
標題: | First Demonstration of CMOS Inverter and 6T-SRAM Based on GAA CFETs Structure for 3D-IC Applications | 作者: | Chang, S.-W. Li, J.-H. Huang, M.-K. Huang, Y.-C. Huang, S.-T. Wang, H.-C. Huang, Y.-J. Wang, J.-Y. Yu, L.-W. Huang, Y.-F. Hsueh, F.-K. Sung, P.-J. Wu, C.-T. Ma, W.C.-Y. Kao, K.-H. Lee, Y.-J. Lin, C.-L. Chuang, R.W. Huang, K.-P. Samukawa, S. Li, Y. Lee, W.-H. Chu, T.-Y. Chao, T.-S. Huang, G.-W. Wu, W.-F. JIUN-YUN LI Shieh, J.-M. Yeh, W.-K. Wang, Y.-H. Lu, D.D. Wang, C.-J. Lin, N.-C. Su, C.-J. Lo, S.-H. Huang, H.-F. |
公開日期: | 2019 | 卷: | 2019-December | 來源出版物: | Technical Digest - International Electron Devices Meeting, IEDM | 會議論文: | 65th Annual IEEE International Electron Devices Meeting, IEDM 2019 | 摘要: | For the first time, CMOS inverters and 6T-SRAM cells based on vertically stacked gate-all-around complementary FETs (CFETs) are experimentally demonstrated. Manufacturing difficulties of vertically stacked source and drain electrodes of the CFETs have been overcome by using junctionless transistors, thereby reducing the number of lithographic steps required. Furthermore, with post metallization treatments, both the voltage transfer characteristics (VTCs) of CMOS inverters and butterfly curves of SRAM show significant improvements due to the symmetry of nMOS and pMOS threshold voltages. Simulation shows that 3-dimensional CFET inverters have lower input parasitic capacitance than standard 2-dimensional CMOS, leading to reduced gate delay and lower power consumption. © 2019 IEEE. |
URI: | https://www.scopus.com/inward/record.url?eid=2-s2.0-85081065128&partnerID=40&md5=0e05e16d4580a733854a39186726db5c https://scholars.lib.ntu.edu.tw/handle/123456789/559061 |
ISSN: | 01631918 | DOI: | 10.1109/IEDM19573.2019.8993525 | SDG/關鍵字: | Capacitance; CMOS integrated circuits; Electron devices; Static random access storage; Threshold voltage; Timing circuits; 6t sram cells; Butterfly curves; CMOS inverters; Junctionless transistors; Lower-power consumption; Parasitic capacitance; Source and drain electrodes; Voltage transfer characteristic (VTCs); Three dimensional integrated circuits |
顯示於: | 電機工程學系 |
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