https://scholars.lib.ntu.edu.tw/handle/123456789/580851
標題: | A 10-bit 300 MS/s pipeline ADC with time-domain MDAC | 作者: | Chen H.-S Tseng C.-J Chuang Y.-W Chang C.-W. HSIN-SHU CHEN |
關鍵字: | Analog to digital conversion; Comparator circuits; Comparators (optical); Operational amplifiers; Pipelines; Conversion rates; Current sources; Input frequency; Low noise comparators; Noise analysis; Pipeline ADCs; Power efficient; Signal subtraction; Time domain analysis | 公開日期: | 2021 | 來源出版物: | Analog Integrated Circuits and Signal Processing | 摘要: | A 10-bit 300?MS/s pipeline ADC utilizing time-domain MDAC is presented. The time-domain MDAC using only current sources and comparators to execute both signal subtraction and amplification is proposed to realize an opamp-less power-efficient structure without calibration. At the conversion rate of 300?MS/s with Nyquist input frequency, the ADC simulated in 40-nm CMOS exhibits an ENOB of 9.38 and 7.96 bits without and with device noise, respectively. It dissipates 19?mW at 1.2?V supply, where one-third of the power is consumed by the low-noise comparator. The noise analysis of the proposed time-domain MDAC is addressed. The active area of the ADC is 0.1?mm2. ? 2021, The Author(s), under exclusive licence to Springer Science+Business Media, LLC, part of Springer Nature. |
URI: | https://www.scopus.com/inward/record.uri?eid=2-s2.0-85105264860&doi=10.1007%2fs10470-021-01858-3&partnerID=40&md5=f56da95c0c992965e2cb0262a39eb127 https://scholars.lib.ntu.edu.tw/handle/123456789/580851 |
ISSN: | 09251030 | DOI: | 10.1007/s10470-021-01858-3 |
顯示於: | 電機工程學系 |
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