https://scholars.lib.ntu.edu.tw/handle/123456789/581494
標題: | Timing-aware fill insertions with design-rule and density constraints | 作者: | Lan T Li X Chen J Yu J He L Dong S Zhu W Chang Y.-W. YAO-WEN CHANG |
關鍵字: | Benchmarking; Capacitance; Monte Carlo methods; Timing circuits; Coupling capacitance; Density constraints; Dielectric thickness; Insertion problems; Manufacturing yield; Optimization method; Process Variation; State of the art; Computer aided design | 公開日期: | 2019 | 卷: | 2019-November | 來源出版物: | IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD | 摘要: | Metal fill insertion has become an essential step to reduce dielectric thickness variation and improve pattern uniformity, which is important in mitigating process variations, thereby achieving better manufacturing yield. However, metal fills could induce coupling capacitance, which is not often considered in existing works that typically focus more on pattern density uniformity, incurring significant problems in timing closure. In this paper, we address the timing-aware fill insertion problem that considers the total capacitance and density constraints simultaneously. First, initial metal fill insertion and design-rule-aware legalization are used to quickly obtain an initial fill insertion solution. Second, from critical conductors to powers/grounds in a circuit, we divide conductors into different equivalent paths and then construct a capacitance graph to globally reduce the capacitance of each equivalent path. Third, we present a density-aware coupling capacitance optimization method and a fast Monte Carlo based fill selection to further reduce the coupling capacitance between any pair of conductors. Finally, we present a density-aware fill deletion method to reduce the fill amounts. We evaluate the performance of our algorithm based on the benchmarks of the 2018 CAD Contest at ICCAD and its official contest evaluator. Compared with the first place team of the contest and the state-of-the-art work, experimental results show that our algorithm achieves the lowest total capacitance and the least fill amount for each benchmark. ? 2019 IEEE. |
URI: | https://www.scopus.com/inward/record.uri?eid=2-s2.0-85077788207&doi=10.1109%2fICCAD45719.2019.8942079&partnerID=40&md5=4ad44ad35c4394ff237fdac0dd0098f9 https://scholars.lib.ntu.edu.tw/handle/123456789/581494 |
ISSN: | 10923152 | DOI: | 10.1109/ICCAD45719.2019.8942079 |
顯示於: | 電信工程學研究所 |
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