| Issue Date | Title | Author(s) | Source | scopus | WOS | Fulltext/Archive link |
| 2017 | A 0.06mm2 ±50mV Range -82dB THD Chopper VCO-based Sensor Readout Circuit in 40nm CMOS | C.-C. Tu; Y.-K. Wang; T.-H. Lin; TSUNG-HSIEN LIN ; 林宗賢 | IEEE Symposium on VLSI Circuits | 16 | 0 | |
| 2001 | 0.24-μm CMOS technology and BSIM RF modeling for bluetooth power applications | Chen, Y.-J.E.; Heo, D.; Laskar, J.; Bien, D.; YI-JAN EMERY CHEN | Microwave Journal | | | |
| 2017 | A 0.3-V 7.6-fJ/conv-step delta-sigma time-to-digital converter with a gated-free ring oscillator | C.-K. Chang; Y.-K. Tsai; K.-H. Cheng; L.-H. Lu; LIANG-HUNG LU | IEEE NEWCAS 2017 | 0 | 0 | |
| 2018 | A 0.5-V 400-MHz Transceiver Using Injection-Locked Techniques in 180-nm CMOS | C.-R. Lee; T.-W. Wang; Y.-L. Tsai; T.-H. Lin; TSUNG-HSIEN LIN ; 林宗賢 | IEEE ICSICT | 0 | 0 | |
| 2016 | A 0.5-V Sub-mW Energy-Efficient Receiver in 0.18-um CMOS for IoT Applications | T.-W. Wang; Y.-L. Tsai; C.-R. Lee; F.-L. Hung; T.-H. Lin; TSUNG-HSIEN LIN ; 林宗賢 | IEEE ISOCC | 0 | 0 | |
| 2009 | A 0.6 V low-power wide-range delay-locked loop in 0.18 ?m CMOS | Lu, Chung-Ting; Hsieh, Hsieh-Hung; Lu, Liang-Hung | IEEE Microwave and Wireless Components Letters | | |  |
| 2017 | A 0.6-V 200-kbps 429-MHz Ultra-low-power FSK Transceiver in 90-nm CMOS | C.-Y. Chiu; Z.-C. Zhang; T.-H. Lin; TSUNG-HSIEN LIN ; 林宗賢 | IEEE A-SSCC | 0 | 0 | |
| 2007 | 0.6伏互補式金氧半導體類比電路之設計與實作 | 魏軍浩; Wei, Chun-Hao | | | | |
| 2017 | A 1-V 5-MHz Bandwidth 68.3-dB SNDR Continuous-Time Delta-Sigma Modulator with a Feedback-Assisted Quantizer | C.-H. Weng; Y.-Y. Lin; T.-H. Lin; TSUNG-HSIEN LIN ; 林宗賢 | IEEE Transactions on Circuits and Systems I | 3 | 7 | |
| 2005 | 1-V 7-mW Dual-Band Fast-Locked Frequency Synthesizer | Vikas Sharma; Chien-Liang Chen; Charlie Chung-Ping Chen; CHUNG-PING CHEN | GLSVLSI | 8 | 0 | |
| 2010 | 1.4μW/channel 16-channel EEG/ECoG Processor for Smart Brain Sensor SoC | T.-C. Chen; T.-H. Lee; Y.-H. Chen; T.-C. Ma; T.-D. Chuang; C.-J. Chou; C.-H. Yang; T.-H. Lin; L.-G. Chen; LIANG-GEE CHEN ; TSUNG-HSIEN LIN | IEEE Symposium on VLSI Circuits | 12 | 0 | |
| 2017 | A 1.5-GHz Sub-Sampling Fractional-N PLL for Spread-Spectrum Clock Generator in 0.18-μm CMOS | C.-Y. Lin; T.-J. Wang; T.-H. Lin; TSUNG-HSIEN LIN ; 林宗賢 | IEEE A-SSCC | 2 | 0 | |
| 2009 | A 10 GHz Phase-Locked Loop With a Compact Low-Pass Filter in 0.18 um CMOS | Li, Sin-Jhih; Hsieh, Hsieh-Hung; Lu, Liang-Hung | IEEE Microwave and Wireless Components Letters | | | |
| 2017 | A 10-Gb/s Equalizer with Digital Adaptation | J-C Hsiao; T-C Lee; TAI-CHENG LEE | International SoC Design Conference | 0 | 0 | |
| 2005 | 100 Mbs OOK transmitter with low power and low phase noise LC VCO for neurosensory application | Upadhyaya, Parag; David, M.Rector; Chen, Yi-Jan Emery | IEEE Southeast Con | 0 | 0 | |
| 2018 | A 10b 2.6GS/s Time-Interleaved SAR ADC with Background Timing-Skew Calibration | C-Y Lin; Y-H Wei; T-C Lee; TAI-CHENG LEE | IEEE Journal of Solid-State Circuits | 21 | 0 | |
| 2016 | A 10b 2.6GS/s Time-Interleaved SAR ADC with Background Timing-Skew Calibration | C-Y Lin; Y-H Wei; T-C Lee; TAI-CHENG LEE | International Solid-State Circuits Conference | 21 | 0 | |
| 2007 | 10GBase-T乙太網路系統晶片設計－子計畫一：經銅線傳輸之百億位元乙太網路系統晶片架構設計(2/3) | 曹恆偉 | | | |  |
| 2008 | 10GBase-T乙太網路系統晶片設計－子計畫一：經銅線傳輸之百億位元乙太網路系統晶片架構設計(3/3) | 曹恆偉 | | | | |
| 2008 | 10GBase-T乙太網路系統晶片設計－子計畫三：適用於10GBase-T乙太網路接收機之類比前端電路(1/2) | 李泰成 | | | | |
