https://scholars.lib.ntu.edu.tw/handle/123456789/607514
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Cai Y.-J | en_US |
dc.contributor.author | Hsu Y | en_US |
dc.contributor.author | YAO-WEN CHANG | - |
dc.creator | Cai Y.-J;Hsu Y;Chang Y.-W. | - |
dc.date.accessioned | 2022-04-25T06:44:14Z | - |
dc.date.available | 2022-04-25T06:44:14Z | - |
dc.date.issued | 2021 | - |
dc.identifier.issn | 0738100X | - |
dc.identifier.uri | https://www.scopus.com/inward/record.uri?eid=2-s2.0-85119455397&doi=10.1109%2fDAC18074.2021.9586296&partnerID=40&md5=59dd3a1fa8a1d35afe1e06b21422da58 | - |
dc.identifier.uri | https://scholars.lib.ntu.edu.tw/handle/123456789/607514 | - |
dc.description.abstract | In modern packaging technology, redistribution layers (RDLs) are often used to redistribute interconnections among multiple chips and between I/O pads and bump pads. For high-density RDL routing, irregular vias, where vias can be placed at arbitrary locations, are adopted to better utilize RDL resources to obtain desired routing solutions. As the problem size increases, however, using irregular vias may suffer from high computation overheads. Moreover, most previous works route pre-assignment (PA) and free-assignment (FA) nets in separate stages, incurring routing resource competition. To remedy these disadvantages, we propose a simultaneous PA and FA routing framework with irregular RDL via planning. In this paper, we first propose a novel partitioning method based on the Voronoi diagram to handle irregular via structures and derive a theoretical upper bound on the number of generated regions. We then propose a chord-based tile model and a net-sequence list to generate non-crossing guides for PA and FA nets on the same routing graph. Finally, we develop a novel geometry-based pattern routing to obtain the final solutions. Experimental results show that our work can achieve 100% routability and an average 30X speedup over the-state-of-the-art work. ? 2021 IEEE. | - |
dc.relation.ispartof | Proceedings - Design Automation Conference | - |
dc.subject | Computation overheads | - |
dc.subject | Density redistribution | - |
dc.subject | Packaging technologies | - |
dc.subject | Partitioning methods | - |
dc.subject | Problem size | - |
dc.subject | Redistribution layers | - |
dc.subject | Resource competitions | - |
dc.subject | Routing frameworks | - |
dc.subject | Routing resources | - |
dc.subject | Routings | - |
dc.subject | Computer aided design | - |
dc.title | Simultaneous Pre-and Free-assignment Routing for Multiple Redistribution Layers with Irregular Vias | en_US |
dc.type | conference paper | en |
dc.identifier.doi | 10.1109/DAC18074.2021.9586296 | - |
dc.identifier.scopus | 2-s2.0-85119455397 | - |
dc.relation.pages | 1147-1152 | - |
dc.relation.journalvolume | 2021-December | - |
item.fulltext | no fulltext | - |
item.openairecristype | http://purl.org/coar/resource_type/c_5794 | - |
item.cerifentitytype | Publications | - |
item.openairetype | conference paper | - |
item.grantfulltext | none | - |
crisitem.author.dept | Electronics Engineering | - |
crisitem.author.dept | Electrical Engineering | - |
crisitem.author.dept | Computer Science and Information Engineering | - |
crisitem.author.dept | Center for Information and Electronics Technologies | - |
crisitem.author.dept | MediaTek-NTU Research Center | - |
crisitem.author.orcid | 0000-0002-0564-5719 | - |
crisitem.author.parentorg | College of Electrical Engineering and Computer Science | - |
crisitem.author.parentorg | College of Electrical Engineering and Computer Science | - |
crisitem.author.parentorg | College of Electrical Engineering and Computer Science | - |
crisitem.author.parentorg | Others: University-Level Research Centers | - |
crisitem.author.parentorg | Others: University-Level Research Centers | - |
顯示於: | 電信工程學研究所 |
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