https://scholars.lib.ntu.edu.tw/handle/123456789/634794
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Lu, C. L. | en_US |
dc.contributor.author | Chuang, C. H. | en_US |
dc.contributor.author | Huang, C. H. | en_US |
dc.contributor.author | Lin, S. C. | en_US |
dc.contributor.author | Chang, Y. H. | en_US |
dc.contributor.author | Lai, W. Y. | en_US |
dc.contributor.author | Chiu, M. H. | en_US |
dc.contributor.author | MING-HAN LIAO | en_US |
dc.contributor.author | Chang, S. Z. | en_US |
dc.date.accessioned | 2023-08-28T06:22:39Z | - |
dc.date.available | 2023-08-28T06:22:39Z | - |
dc.date.issued | 2023-01-01 | - |
dc.identifier.isbn | 9784863488069 | - |
dc.identifier.issn | 07431562 | - |
dc.identifier.uri | https://scholars.lib.ntu.edu.tw/handle/123456789/634794 | - |
dc.description.abstract | Different from Chip on Wafer stacking technology, Wafer on Wafer (WoW) stacking can provide a tighter pitch and higher interconnect density with higher through-put. The difficulty for WoW stacking is on wafer surface and edge treatment. In this work, a 4-layer WoW stacking architecture on 12 -inch wafers with hybrid bonding/bump-less and through-silicon-via (TSV) middle techniques for enabling various 3D integration has been demonstrated and proposed. It projects > 15 % form factor and > 10 % interconnection resistance reduction than typical scheme. Low process temperature (180°C-250°C) is implemented for whole stacking process. Depending on different applications, both of wafers by Face to Face (F2F) and Face to Back (F2B) stacking processes are developed. For bump-less HBM-like structure, it needs special temporary bond and de-pond process for F2B bonding. F2F bonding can present a high dense interconnection for logic to memory AI computing application. The results of 4 layers (TSV x 3 and hybrid bond interface x 3) show that interconnection resistance is < 0.25 Ω per loop. It contains 17Kea of TSVs (5 E 3 / mm2) and 230Kea of hybrid bond pads (2 E 5 / mm2). From the eye-diagram and insertion loss simulation, hybrid bond/bump-less scheme leads to ∼ 40 % performance improvement than it in the bump scheme. | en_US |
dc.relation.ispartof | Digest of Technical Papers - Symposium on VLSI Technology | en_US |
dc.title | 4-Layer Wafer on Wafer Stacking Demonstration with Face to Face/Face to Back Stacked Flexibility Using Hybrid Bond/TSV-Middle for Various 3D Integration | en_US |
dc.type | conference paper | en_US |
dc.identifier.doi | 10.23919/VLSITechnologyandCir57934.2023.10185308 | - |
dc.identifier.scopus | 2-s2.0-85167627146 | - |
dc.identifier.url | https://api.elsevier.com/content/abstract/scopus_id/85167627146 | - |
dc.relation.journalvolume | 2023-June | en_US |
dc.relation.pageend | 2 | en_US |
item.openairetype | conference paper | - |
item.openairecristype | http://purl.org/coar/resource_type/c_5794 | - |
item.fulltext | no fulltext | - |
item.grantfulltext | none | - |
item.cerifentitytype | Publications | - |
crisitem.author.orcid | 0000-0003-2942-4520 | - |
顯示於: | 機械工程學系 |
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