Monocrystalline Region Improvement and Defects Control of N-type Mono-like Silicon Ingot Grown by Directional Solidification
|Keywords:||N 型矽晶;類單晶;缺陷控制;界面控制;太陽能電池;N-type silicon;mono-like silicon;defect control;interface control;solar cell||Issue Date:||2016||Abstract:||
在所有鑄造的矽晶中，N 型類單晶矽擁有高效能與低成本的優勢，然而仍需要在長晶中控制晶碇的阻值、單晶比例以及缺陷的生成。本文主要提到單晶比例與缺陷控制的結果。單晶比例控制部分，藉由加強坩堝側壁保溫可獲得微凸的長晶界面，而在晶種外環排列生成的Σ5晶界可有效阻檔從坩堝側壁成核的多晶，結合以上兩者的方法，單晶比例有明顯的提升且頂部單晶比例可達93%。 缺陷控制部分，第一個晶種排列實驗，將兩個(100)晶種堆疊以防止晶種發生過融，並且控制融料界面橫跨兩個晶種的縫隙進而生成0°晶界。第二個晶種排列實驗，將一個(100)晶種切成一塊圓型晶種以及九塊扇形晶種，並將圓型晶種放置中央，且藉由九塊扇形晶種重新排列生成0°到40°的晶界，討論晶界以及三接點(Triple junction)處角度的變化與缺陷密度的發展。 吾人發現不同縫隙尺寸生成的0°晶界皆會形成小角度晶界且伴隨高缺陷密度，然而切口形成的0°晶界(Σ1)因為晶種間沒有角度差所以沒有發展成小角度晶界。10°到40°大角度晶界缺陷密度明顯較0°晶界低，10°晶界(non-Σ)、20°晶界(Σ13a+ Σ37a)與30°晶界(Σ17a)等低對稱性晶界其缺陷密度比高對稱性的40°晶界(Σ5)低，晶種間最佳旋轉角度應該在20°附近。晶片經過去疵與鈍化處理後，除了0°晶界以外，晶片整體少數載子壽命有明顯提升，且少數載子壽命最高可達3 ms以上。吾人更發現三接點上晶界的缺陷密度比遠離三接點的晶界低，但若三接點中存在高對稱性的晶界，則另兩個晶界的缺陷密度會增加。
Comparing to other type of casting silicon, n-type mono-like casting silicon has advantages of high solar cell efficiency and low cost. But it needs to control the resistivity, monocrystalline area and defect formation during crystal growth. We studied the results of monocrystalline area control and defect control. For monocrystalline area control, we could obtain convex growth interface by improving the insulation of the crucible sidewall. Σ5 GB, which was obtained from arrangement manually at the outer ring of the seed, successfully suppressed the grains nucleated at the crucible sidewalls. By combining these two conditions, we could increase the monocrystalline region and obtain 93% of monocrystalline ratio on top of the ingot. For defect control, the first experiment of the seed arrangement was stacking two (100) seeds while keeping the initial growth front across the seed junction. In the second experiment, the seeds were rearranged from the nine sectors cut from a (100) seed, while keeping a round seed at the center, so different tilt angles between seed sectors were from 0 o to 40o. We further observed the evolution of dislocations near grain boundaries (GBs) and triple junctions (TJs). Our results revealed that the defects generated easily from the 0° GBs regardless of the seed gaps. However, no significant defects generated near the overcut region (Σ1). On the contrary, the large angle GBs (10° to 40° GBs) had little influence on the defect generation. 10° GB (non-Σ), low symmetrical 20° GB (Σ13a+ Σ37a) and 30° GB (Σ17a) resulted in lower dislocation density compared to high symmetrical 40° GB (Σ5), and the optimum tilt angle was around 20°. Gettering and passivation was further performed for the wafers. The high lifetime was obtained except near the 0° seed junction, and the highest lifetime was greater than 3 ms. Furthermore, dislocation density of GBs in TJs were lower than the one away from TJs. The existence of high symmetrical GBs at the TJs resulted in higher dislocation density nearby the rest of GBs at the TJs.
|Appears in Collections:||化學工程學系|
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