Design and Fabrication of CMOS Displacement Capacitive Sensors
Date Issued
2009
Date
2009
Author(s)
Liu, Shih-Yu
Abstract
The theme of the thesis is to discuss the relation of the output voltage and the variance of capacitance about CMOS displacement capacitive sensors. Design and completion of the layout is the first step of the procedure flow. According to the layout the IC is taped out. The last step is to measure and to analyze the signals from every nodes. Through the whole procedure flow, the components which are workable can be defined. This circuit is composed of folded-cascode amplifiers and dispersed elements. The chip can be measured after taping out the IC. In this thesis, we apply 0.35 Mixed-Signal 2P4M Polycide 3.3/5V manufacture process of TSMC which is provided by NSC Chip Implementation Center. Finally, we use Hspice software designed by Synopsys co. to simulate and laker software designed by Springsoft co. to layout the circuit.
Subjects
capacitive sensor
analog integrated circuit
folded-cascode amplifier
IC design
layout
Type
thesis
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