劉深淵臺灣大學：電子工程學研究所林家良Lin, Chia-LiangChia-LiangLin2007-11-272018-07-102007-11-272018-07-102005http://ntur.lib.ntu.edu.tw//handle/246246/57277在深次微米的互補式金氧半導體電路中，在類比數位轉換器的實現上，高速的追蹤保持電路是一個基本且不可或缺的元件，追蹤保持電路的架構可分為兩大類，一是閉迴路的架構，另一類則是開迴路的架構。閉迴路架構的追蹤保持電路擁有高解析度的特性，但是，其取樣速度卻無法達到太快，開迴路架構的追蹤保持電路則是相反，擁有較高速的取樣速度，但卻無法擁有較高的解析度。這兩種電路在目前只能視用途目的而使用不同的架構，並無法有同時擁有兩者兼顧的優點。 在此論文研究當中，一個五位元每秒一百億次的追蹤保持電路在0.18微米互補式金氧半導體製程已經被設計出來。我們提出了一種以開迴路架構為原則的電路，利用電晶體高頻特性，將因為高頻效應所導致的非線性現象降低，加以提升在高速操作下的解析度。In CMOS circuits, a high-speed track-and-hold circuit is a fundamental and indispensable component in an A/D converter. The track-and-hold amplifier can be classified as the open-loop and the closed-loop architectures. The closed-loop architecture has the characteristic of higher resolution and lower speed. On the contrary, the open-loop architecture has the characteristic of lower resolution and higher speed. Consequently, different kinds of track-and-hold circuits will be needed based on the purpose of the applications. Now no architecture can have both the advantages at the same time. In this thesis, a 5-bit 10Gb/s track-and-hold circuit has been designed and implemented in a standard 0.18-um CMOS process. It utilizes the high frequency characteristic of MOS transistors to reduce the nonlinearity due to the effect of high-frequency and raise the resolution under high-frequency operation.1 Introduction 1 1.1 Background………………………………………………………… 1 1.2 Motivation………...……………………………………………….. 3 1.3 Thesis Organization………………………………………………... 3 2 Fundamentals of Track-and-Hold Circuit 5 2.1 THA Performance Metrics………………………………………… 5 2.1.1 Total Harmonic Distortion (THD)………………………… 5 2.1.2 Signal to Noise Ratio……………………………………… 6 2.1.3 Signal to Noise Distortion Ratio………………………....... 8 2.1.4 Resolution…………………………………………………. 9 2.2 The Concept of Track-ad-Hold Circuits…………………………… 9 2.2.1 MOS switches……………………………………………... 9 2.2.2 Charge injection…………………………………………… 11 2.2.3 Clock Feedthrough………………………………………… 13 2.3 THA architecture.………………………………………………….. 14 2.3.1 Complementary Switch…………………………………… 14 2.3.2 Bootstrapped Switch………………………………………. 16 2.4 Application in the pipelined ADC…………………………………. 18 2.5 Application in the pipelined ADC…………………………….…… 20 3 A 5-bit 10-Gb/s Track-and-Hold Circuit 23 3.1 Motivation…………………………………..……………...……… 23 3.2 Architecture…………………...……………………………………. 24 3.3 Circuit Design…………………………………………………...…. 26 3.3.1 THA………………………………………………………... 26 3.3.2 PMOS Source Follower……………………………………. 33 3.3.3 Adder……………………………………………………….. 34 3.3.4 Output buffer……………………………………………….. 36 3.4 Simulation Results…………………………...…………………….. 36 3.5 Measurement…………………………..…………………………… 39 3.5.1 Transient Response………………………………………… 39 3.5.2 FFT measurement result 41 3.5.3 Beat frequency test measurement result 45 4 Conclusion 49 4.1 Conclusion…………………..………………………………...…… 49 Bibliography 511787107 bytesapplication/pdfen-USAnalog-to-digital conversiontrack-and-hold amplifiercompensation類比數位轉換器追蹤保持放大器補償thesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/57277/1/ntu-94-R92943103-1.pdf