2.8 to 67.2mW low-power and power-aware H.264 encoder for mobile applications

Chen, T.-C.T.-C.ChenChen, Y.-H.Y.-H.ChenTsai, C.-Y.C.-Y.TsaiTsai, S.-F.S.-F.TsaiSHAO-YI CHIENLIANG-GEE CHEN2018-09-102018-09-102007https://www.scopus.com/inward/record.uri?eid=2-s2.0-39749116345&doi=10.1109%2fVLSIC.2007.4342727&partnerID=40&md5=2f852b5b09db7780bb51cfb8f9dd8849http://scholars.lib.ntu.edu.tw/handle/123456789/332261A 2.8 to 67.2mW H.264 encoder is implemented on a 12.8mm2 die with 0.18μm CMOS technology. The proposed parallel architectures along with fast algorithms and data reuse schemes enable 77.9% power savings. The power awareness is provided through a flexible system hierarchy that supports content-aware algorithms and module-wise gated clock.Algorithms; Data processing; Reusability; Data reuse schemes; Gated clock; Mobile applications; System hierarchy; CMOS integrated circuits2.8 to 67.2mW low-power and power-aware H.264 encoder for mobile applicationsconference paper10.1109/VLSIC.2007.43427272-s2.0-39749116345