吳瑞北臺灣大學:電信工程學研究所徐巳烜Hsu, Ssu-HsuanSsu-HsuanHsu2010-07-012018-07-052010-07-012018-07-052008U0001-1308200814331200http://ntur.lib.ntu.edu.tw//handle/246246/188191本論文主要是針對電源完整度的問題做探討。電源接地平面中，最主要的雜訊來自於信號線在穿過多層板時，引發層板間的接地彈跳雜訊。為了避免雜訊在層板間傳播導致電壓浮動、邏輯位準誤判，本論文採用了基因演算法結合三角網格電源接地平面模型，來針對實際不規則形狀的電源接地平面，完成指定位置的去耦合電容之最佳化。論文利用簡單的模型描述多層板的低頻特性，並探討短路連通柱對於電源完整度所造成的影響，最後針對矩形的結構提出一連通柱擺置的設計準則，以達到保持多層板電源完整度之目的。The major theme of this thesis is focused on the problem of power integrity. Power integrity is a crucial issue to the stability of entire system. As noticed of the ground bounce noise for the primary noise of power-ground planes, it comes from the transition of signal current through a via which radiates the electromagnetic waves between planes. In order to avoid the voltage fluctuation, leading to misjudgment of digital signal, this thesis combines the genetic algorithm with the triangular-mesh scheme to model the power-ground planes, and thus optimizes the placement of decoupling capacitors on the specified locations for a realistically irregular-shaped geometry.his thesis discusses the low-frequency responses of multi-layered structures using a simple model which describes the effect of shorting vias on power integrity. Finally, the design rule of the placement of shorting vias is proposed to maintain the power integrity of multi-layered structures.摘要 Ibstract III錄 V一章 簡介 1.1 研究動機 1.2 文獻探討 4.3 貢獻 5.4 章節概要 5二章 接地彈跳雜訊之成因與常見抑制方式 7.1接地彈跳雜訊現象與成因 7.2常見抑制接地彈跳雜訊方式 7.3電源接地平面模型介紹 9三章 去耦合電容最佳化設計 21.1基因演算法簡介 21.2成本函數定義 24.3去耦合電容最佳化模擬結果 29四章 多層板之等效電路與短路連通柱擺置 33.1多層板等效電路模型化與理論推導 33.2短路連通柱對於電源完整度影響 38.3短路連通柱之擺置 41五章 結論 47考文獻 491765552 bytesapplication/pdfen-US電源完整度去耦合電容短路連通柱Power IntegrityDecoupling CapacitorShorting Viathesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/188191/1/ntu-97-R95942063-1.pdf