Jiang I.H.-RChang Y.-WHuang J.-LCHUNG-PING CHENHUI-RU JIANGJIUN-LANG HUANGYAO-WEN CHANG2021-09-022021-09-02202010923152https://www.scopus.com/inward/record.uri?eid=2-s2.0-85097955684&doi=10.1145%2f3400302.3415767&partnerID=40&md5=552cbb8be2bed3d3a8dac18d666d6ed4https://scholars.lib.ntu.edu.tw/handle/123456789/580769As the design complexity grows dramatically in modern circuit designs, 2.5D/3D chip/package/board integration has become a key to beat process limitation for optimizing system performance and power consumption. Among the explored technologies, the wafer-level integrated fan-out (InFO) package-on-package (PoP) has been adopted by major companies such as TSMC to achieve high-density, high-performance, low-cost packaging solutions. To achieve a high-quality 2.5D/3D heterogeneous integration system, we shall study the chip, package, and board codesign methodology with advanced packages and explore key techniques to handle the emerging challenges in physical design, timing, electrical effects, and testing. ? 2020 Association on Computer Machinery.Chip scale packages; Computer aided design; Costs; Indium compounds; Integration; Integration testing; Printed circuit design; Programmable logic controllers; System-on-chip; Co-design methodology; Design complexity; Electrical effects; Heterogeneous integration; Intelligent designs; Low-cost packaging; Package on packages; SOC integration; Integrated circuit designconference paper10.1145/3400302.34157672-s2.0-85097955684