Chang, Chih-ChiaChih-ChiaChangYu, Hung-ShuHung-ShuYuPEI YUN TSAI2025-08-052025-08-052025-05-2502714310https://www.scopus.com/pages/publications/105010621535https://scholars.lib.ntu.edu.tw/handle/123456789/730959Conference date:25 May 2025 - 28 May 2025A configurable fast Fourier transform (FFT) processor capable of computing composite power points becomes prevailing in recent communication and signal processing systems. In this paper, a continuous-flow memory-based FFT processor is designed to support 63 modes from 32 to 4096 points. A conflict-free and in-place addressing scheme is proposed to minimize the number of memory banks and total memory sizes for input buffering, intermediate storage, and output re-ordering. The processing element handles radix-3, radix-4, radix-5, radix-(4•2), radix- 32, radix-42 butterflies using a multi-path delay commutator (MDC) architecture with up to five parallel paths. Besides, the 3-tuple multi-radix representation is adopted for the virtual address generation and thus we can extend the concept of conventional conflict-free and in-place addressing for physical address and bank assignments beyond power-of-2 cases. From the comparison results, our proposed FFT processor architecture demonstrates strong computational efficiency by considering both the arithmetic complexity of butterfly operations and twiddle-factor multipliers as well as throughput.falseConflict-free addressingin placememory-based FFTmixed-radixconference paper10.1109/iscas56072.2025.110438432-s2.0-105010621535