Wu, Bing-ChenBing-ChenWuTSUNG-TE LIU2020-06-112020-06-112019https://scholars.lib.ntu.edu.tw/handle/123456789/499789https://www.scopus.com/inward/record.uri?eid=2-s2.0-85073752233&doi=10.1109%2fIOLTS.2019.8854384&partnerID=40&md5=617180f74c1154d1334b127336c8b372Process, voltage, and temperature (PVT) variations substantially increase the variability of digital CMOS logics and reduce the operation robustness, especially for energy-constrained systems with aggressive voltage scaling. This paper reviews several variation-resilient design techniques for addressing PVT variations to improve the energy efficiency of digital CMOS VLSI circuits. The scope includes static and adaptive design techniques for design-time and run-time optimization, respectively. In addition, an emerging adaptive design strategy combining the fully integrated voltage regulator for system-level optimization is also introduced. © 2019 IEEE.adaptive design.; and temperature (PVT) variations; Fully integrated voltage regulator; process; variation-resilient techniques; voltage[SDGs]SDG7CMOS integrated circuits; Electric potential; Energy efficiency; Processing; Systems analysis; Voltage regulators; Voltage scaling; Adaptive design techniques; Adaptive designs; Aggressive voltage scaling; and temperature (PVT) variations; Energy constrained systems; Fully integrated; System level optimization; variation-resilient techniques; Integrated circuit designconference paper10.1109/IOLTS.2019.88543842-s2.0-85073752233https://doi.org/10.1109/IOLTS.2019.8854384