國立臺灣大學電子工程學研究所闕志達2006-07-262018-07-102006-07-262018-07-102005http://ntur.lib.ntu.edu.tw//handle/246246/20061在本年度中，我們提出了兩個晶片 之實做：(1)適用於不規則低密度奇偶檢 查碼(LDPC)之可重配置解碼器晶片(2)混 合信號耙式(Rake Receiver)接收機。在(1) 中，我們從研究演算法開始著手，接著 設計了一套硬體架構來實現演算法，同 時兼顧可重配置的需求。接著進行系統 模擬，並與Soft Viterbi 解碼演算法比較彼 此的效能優劣。現在正在進行硬體實現 的步驟，主要是同時進行晶片的數位電 路部分之RTL 程式與記憶體電路方面的 全客戶式佈局設計。在(2)中，我們提出 以類比電路來實做耙式接收機的方式。 一方面其所消耗的功率較數位的耙式接 收機為少，另一方面藉由整合類比相關 器而減少系統類比轉數位信號轉換器功 率之消耗。目前正在進行類比電路部分 及系統的符元錯誤率模擬。In this year, we propose the implementation of two chips. (1) A reconfigurable decoder IC for Irregular LDPC codes. (2) A mixed signal Rake receiver. In (1), we started from surveying the decoding algorithms of LDPC, and designed a hardware architecture to implement the decoding algorithm and meet the reconfigurable requirement. Afterwards, we did the system simulation and compared the performance with the Viterbi decoding algorithm. Now we are doing the step of hardware implementation including the RTL coding of the digital circuit and the full-custom design of memory blocks. In (2), we proposed an analog Rake receiver. It can lessen the receiver power consumption as compared to digital Rake receiver and maintain the advantage of the overall system by incorporating the analog correlator to reduce the power consumption of analog to digital converter.application/pdf322085 bytesapplication/pdfzh-TW國立臺灣大學電子工程學研究所不規則低密度奇偶檢查 碼可重配置解碼器晶片混合信號耙式接收機類比轉數位信號轉換器Irregular Low-density Parity Check CodeReconfigurable Decoder ICAnalog to Digital Converterreporthttp://ntur.lib.ntu.edu.tw/bitstream/246246/20061/1/932220E002013.pdf