Hsieh, Yong-HsiangYong-HsiangHsiehHu, Wei-YiWei-YiHuLin, Shin-MingShin-MingLinChen, Chao-LiangChao-LiangChenLi, Wen-KaiWen-KaiLiSAO-JIE CHENChen, D.J.D.J.Chen2009-03-112018-07-062009-03-112018-07-06200500189200http://ntur.lib.ntu.edu.tw//handle/246246/144091https://www.scopus.com/inward/record.uri?eid=2-s2.0-27844470557&doi=10.1109%2fJSSC.2005.857348&partnerID=40&md5=fba0a696ee0b317982f086a6b5bc5bf7The CMOS transceiver IC exploits the superheterodyne architecture to implement a low-cost RF front-end with an auto-J/Q calibration function for IEEE 802.11g. The transceiver supports I/Q gain and phase mismatch auto tuning mechanisms at both the transmitting and receiving ends, which are able to reduce the phase mismatch to within 1° and gain mismatch to 0.1 dB. Implemented in a 0.25 μm CMOS process with 2.7 V supply voltage, the transceiver delivers a 5.1 dB receiver cascade noise figure, 7 dBm transmit, and a 1 dB compression point. © 2005 IEEE.application/pdf1086155 bytesapplication/pdfen-US802.11g; Auto calibration; DC offset cancellation; Gain mismatch; Phase mismatch; RF transceiver802.11g; Auto calibration; DC offset cancellation; Gain mismatch; Phase mismatch; RF tranceiver; Calibration; CMOS integrated circuits; Data compression; Gain control; Heterodyning; Spurious signal noise; Transceiversjournal article2-s2.0-27844470557http://ntur.lib.ntu.edu.tw/bitstream/246246/144091/1/26.pdf