A bist RAM architecture with parallel testing in a microprogram ROM

Huang, J.-M.J.-M.HuangFEI-PEI LAI2020-04-162020-04-161993https://scholars.lib.ntu.edu.tw/handle/123456789/484475A bist RAM architecture with parallel testing in a microprogram ROMjournal article10.1080/02533839.1993.96775422-s2.0-0027664066https://www.scopus.com/inward/record.uri?eid=2-s2.0-0027664066&doi=10.1080%2f02533839.1993.9677542&partnerID=40&md5=32255a74285a3690928d99c6b955c0b8