黃鐘揚臺灣大學:電子工程學研究所張啟文Chang, Chi-WenChi-WenChang2007-11-272018-07-102007-11-272018-07-102007http://ntur.lib.ntu.edu.tw//handle/246246/57552高階設計資訊被廣泛的應用在現今超大型積體電路的設計上,如:有限狀態機、計數器等等。我們可利用這些高階資訊去輔助設計空間的延展,進一步改善驗證的效率及品質。然而,幾個已存在著眼於高階資訊箤取的相關研究中,都僅能在限定的描述格式下箤取出非常有限的控制結構,如:明確型有限狀態機。在這篇論文中,我們提出一個新穎的技術,能夠精確地箤取出所有的結構,如:明確型有限狀態機、隱含型有限狀態機及計數器。我們於論文中證明幾個演算法中的定理,表示出我們提出的演算法是非常有用的,且不會因為描述方式不同而限制其能力,更不會被侷限在可合成的語法的框架下。在實驗時,我們實際測試幾個真正的設計去呈現出我們的程式在常見的商業化軟體中,依然處於優先的角色。High-level design intents such as finite state machine (FSM) and counter are commonly used in modern VLSI design. We can use them to guide the exploration of the design space and thus improve the verification efficiency. However, previous works on high-level intent extraction can only identify very limited constructs such as explicit FSM in restricted coding style. In this work, we propose a novel technique which can extract all the explicit, implicit FSMs and the counter. We also prove with several theorems that our algorithms are very robust and not limited to the coding styles and the HDL synthesizable subset. The experimental results on several real designs demonstrate that our program is superior over existing commercial tools.摘要 i Abstract ii Acknowledgements iii List of Tables vi List of Figures vii Chapter 1 Introduction 1 Chapter 2 Definitions and Examples 4 Chapter 3 High-Level Design Intent Extraction 10 3.1 Overview of the Extraction Algorithm 10 3.2 HDL Analysis 11 3.3 Explicit FSM Extraction 14 3.3.1 State Register Recognition of explicit FSM 14 3.3.2 Reset State Recognition of Explicit FSM 15 3.3.3 STG Generation of Explicit FSM 16 3.4 Implicit FSM Extraction 17 3.4.1 State Register Recognition of Implicit FSM 17 3.4.2 Reset state recognition of implicit FSM 18 3.4.3 STG generation of implicit FSM 18 3.5 Counter Extraction 19 3.6 Hybrid FSM 20 3.7 FSM Analysis 21 3.8 Data Structure 22 3.8.1 Signal 22 3.8.2 Finite State Machine 23 3.8.3 Counter 24 Chapter 4 Experimental Result 26 Chapter 5 User Interface 32 5.1 Command Line Interface 32 5.2 Graphic User Interface 33 Chapter 6 Case Study 36 Chapter 7 Applications and Future Work 40 References 42 Appendix I Reference Manual 432419710 bytesapplication/pdfen-US有限狀態機暫存器轉移層設計資訊箤取FSM RTLDesign IntentExtraction智慧型驗證之高階設計資訊箤取技術High-Level Design Intent Extraction for Intelligent Verificationthesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/57552/1/ntu-96-R94943066-1.pdf