Shyu, MichaelMichaelShyuChang, Yu-DongYu-DongChangWu, Guang-MingGuang-MingWuYAO-WEN CHANG2018-09-102018-09-101999http://www.scopus.com/inward/record.url?eid=2-s2.0-0033300355&partnerID=MN8TOARShttp://scholars.lib.ntu.edu.tw/handle/123456789/350375A switch block M with W terminals on each side is said to be universal if every set of nets satisfying the dimension constraint (i.e., the number of nets on each side of M is at most W) is simultaneously routable through M (Y.W. Chang et al., 1996). We present an algorithm to construct N-sided universal switch blocks with W terminals on each side. Each of our universal switch blocks has (/sub 2//sup N/)W switches and switch-block flexibility N-1 (i.e., F/sub S/=N-1). We prove that no switch block with less than (/sub 2//sup N/)W switches can be universal. Further, the decomposition property of a universal switch block provides a key insight into its layout implementation with a smaller silicon area. We also compare our universal switch blocks with others of the topology associated with Xilinx XC4000-type FPGAs. Experimental results demonstrate that our universal switch blocks improve routability at the chip level.[SDGs]SDG9conference paper10.1109/ICCD.1999.8085572-s2.0-0033300355