陳中平臺灣大學：電子工程學研究所陳建良Chen, Chien-LiangChien-LiangChen2007-11-272018-07-102007-11-272018-07-102004http://ntur.lib.ntu.edu.tw//handle/246246/57344論文裡我們設計了一伏特的低雜訊放大器、LC共振腔壓空振盪器以及頻率合成器。主要在低電壓、低功率以及小體積的設計。於是我們完成了一個S11 為 -20dB@5GHz， S21 為 7dB@5GHz以及 NF 為is -3.2dB@5GHz的一伏特低雜訊放大器。以及KVCO 為 700MHz/V 和相位雜訊為-100dBc@100KHz的一伏特壓控振盪器，最後是一個擁有雙頻切換的一伏特頻率合成器。In this work at first a thorough study of WLAN, 802.11a has been done. And then we have explored different architecture for the LNA, VCO, and Frequency Synthesizer. Architecture details and circuit modification are elaborately described in the chapters concerned. As we know that for wireless communication systems, the power consumption and the cost per chip are very important factors. Even though there may be many variations in practice, we find a high degree of commonality in the RF stages of most wireless systems. Therefore we focused our research to design, propose and/or improve every circuit structure so that they can work well under only 1-Volt power supply. Reduction in power consumption and continuous technology scaling are the reason to choose 1- volt power supply. So we first designed a 1-Volt LNA with S11 is -20dB@5GHz, S21 is 7dB@5GHz, and NF is -3.2dB@5GHz. Second a 1-Volt VCO with KVCO is 700MHz/V and Phase Noise is -100dBc@100KHz. Final the PLL intended for wireless LAN applications can synthesize frequencies in 2.4GHz in step of 9.375 MHz and between 5.14 and 5.70 GHz in steps of 20 MHz. The reference spurs at 10-MHz offset are as low as 80 dBc, and the phase noise at 1 MHz is lower than 118 dBc/Hz for the entire tuning range.Table of Contents Acknowledgements Ⅰ Abstracts Ⅲ Table of Contents IV List of Figures List of Tables Chapter 1　Introduction 1 1.1　Motivation 1 1.2　An overview of an transceiver 1 1.3　Thesis Overview 2 Chapter 2　Receiver Architecture 4 2.1　Basic Concepts 4 2.1.1　Motivations 4 2.1.2　General Design Philosophy 5 2.1.3　Introduction to Wireless System Components 7 2.1.3.1　Basic Radio System 7 2.1.3.2　Antennas 8 2.1.3.3　Filters 8 2.1.3.4　Amplifiers 9 2.1.3.5　Mixers 9 2.1.3.6　Oscillators 9 2.2　Nonidealities and Design Parameter 10 2.2.1　Thermal Noise 10 2.2.2　Flicker Noise 10 2.2.3　Noise Temperature and Noise Figure 11 2.2.3.1　Equivalent Noise Temperature 12 2.2.3.2　Measurement of Noise Temperature 13 2.2.3.3　Noise Figure 14 2.2.3.4　 Noise Figure of Cascaded Components 16 2.2.4　Dynamic Range and Intermodulation Distortion Noise Figure 18 2.2.4.1　Gain Compression 19 2.2.4.2　Intermodulation Distortion 20 2.2.4.3　Third-Order Intercept Point 22 2.2.4.4　Dynamic Range 24 2.2.4.5　Intercept Point of Cascaded Components 25 Chapter 3　1-Volt Low-Noise Amplifier 28 3.1　General Philosophy 28 3.2　Matching Networks 30 3.2.1　Introduction 30 3.2.2　Matching for noise and stability 30 3.2.3　Matching for power 31 3.3　Stability 33 3.4　1-Volt Low Noise Amplifier Design 33 3.4.1　Circuit Design 33 3.4.2　Simulation Result 35 3.4.3　Experimental Result 36 Chapter 4　1-Volt Voltage-Controlled Oscillator 38 4.1　Design Parameter 39 4.2　Oscillator Theory 39 4.3　Quality Factor of the LC-Tank Oscillator 42 4.4　Architectures of the LC-tank VCOs 43 4.5　Phase Noise Overview 45 4.5.1　Definition of Phase Noise 45 4.5.2　Review of Phase Noise Analysis 46 4.6　Phase Noise Models 46 4.6.1　Leeson's Linear Time Invariant Model 47 4.6.2　J.J. Rael's Improved Equation 49 4.6.3　Ali's Linear Time Variant Model 52 4.6.3.1　Linear Time Variant Assumption 52 4.6.3.2　Impulse Sensitivity Function 54 4.6.3.3　Ali’s Equation 55 4.7　Design of the 1-Volt Voltage Controlled Oscillator 58 4.7.1　Design Flow 59 4.7.2　Simulation Result 60 4.7.3　Experimental Result 63 Chapter 5　1-Volt Dual-Band Tri-Mode Fast-Locked Frequency Synthesizer 65 5.1　Phase-Locked Loop (PLL) Fundamentals 65 5.1.1　Voltage-controlled Oscillator (VCO) 65 5.1.2　Phase-Frequency Detector (PFD) 66 5.1.3　Charge-Pump (CP) 67 5.1.4　Loop Filter (LF) 68 5.1.5　Frequency Divider 69 5.1.3　Charge-Pump (CP) 67 5.2　Charge-Pump PLL System Design 72 5.2.1　Second-Order PLL 72 5.2.2　Third-Order PLL 75 5.2.3　Fourth-Order PLL 78 5.3　Phase Noise Performance Analysis 80 5.3.1　Noise at Input 80 5.3.2　Noise of VCO 81 5.4　Basic Blocks of PLL based Frequency Synthesizer 82 5.4.1　Phase Frequency Detector (PFD) 83 5.4.2　Charge Pump (CP) & Loop Filter (LF) 85 5.4.3　High-Frequency Dual-Modulus Prescaler 87 5.4.3.1　Architecture 87 5.4.3.2　Circuit description 88 5.4.3.3　Input preamplifier 90 5.4.4　Simulation Result 91 Chapter 6　Conclusions 93 6.1　Conclusions 93 Bibliography List of Figures Chapter 1 Figure 1.1 The whole transceiver. 2 Chapter 2 Figure 2.1　　Front end of the receiver enclosed in dotted line. 4 Figure 2.2　　Block diagram symbols for commonly used RF and microwave components. 7 Figure 2.3　　Block diagram of a basic radio receiver system. 8 Figure 2.4　　(a)Thermal noise of a resistor and (b)thermal noise of a MOSFET. 10 Figure 2.5　　Concept of flicker noise corner frequency. 11 Figure 2.6　　Equivalent noise temperature of an arbitrary white noise source. 11 Figure 2.7　　Equivalent noise temperature of a noisy amplifier(a)noisy amplifier and (b)equivalent noiseless amplifier. 12 Figure 2.8　　The Y-factor method for measuring equivalent noise temperature. 14 Figure 2.9　　Relating the noise figure of a noisy network to its equivalent noise temperature. 15 Figure 2.10　 Noise figure and equivalent noise temperature of a cascaded system (a) two cascaded networks and (b) equivalent network. 16 Figure 2.11　 A general nonlinear device or network. 17 Figure 2.12　 Definition of the 1dB compression point for a nonlinear amplifier. 17 Figure 2.13　 Output spectrum of second and third-order two-tone intermodulation products, assuming ω1<ω2. 22 Figure 2.14　 Third-order intercept diagram for a nonlinear component. 23 Figure 2.15　 Illustrating linear dynamic range and spurious free dynamic range. 25 Figure 2.16　 Third-order intercept point for a cascaded system (a) two cascaded networks and (b) equivalent network. 26 Chapter 3 Figure 3.1　　Generalized LNA topology. 29 Figure 3.2　　Lumped parameter representation of amplifier. 29 Figure 3.3　　LNA using lumped parameter representation. 33 Figure 3.4　　Cascoded LNA. 34 Figure 3.5　　Small signal model of the cascoded LNA. 35 Figure 3.6　　S parameter simulation result of the LNA.. 35 Figure 3.7　　NF simulation result of the LNA. 36 Figure 3.8　　Die photo of the LNA. 36 Figure 3.9　　S parameter measure result of the LNA. 37 Figure 3.10　 NF measure result of the LNA. 37 Chapter 4 Figure 4.1　　Block diagram of a Feedback System. 40 Figure 4.2　　(a)LC oscillators.(b)Simplify diagram. 41 Figure 4.3　　Conversion of a series combination to a parallel combination. 42 Figure 4.4　　(a) The NMOS-only cross-coupled oscillator and (b) complementary cross-coupled topology and (c) the Colpitts oscillator and (d) transfer function of the Colpitts oscillation. 43 Figure 4.5　　(a) The spectrum of the ideal sinusoidal wave and (b) definition of phase noise. 46 Figure 4.6　　Ideal model of RLC oscillator. 48 Figure 4.7　　Phase noise spectrum of the LC oscillator according to Leeson. 49 Figure 4.8　　(a) Noise at input of differential pair modulates instants of zero crossing and (b) output current consists of square wave, plus random noise pulses and (c) noise pulses modeled as a train of impulses sampling noise waveform. 50 Figure 4.9　　X: the magnitude of impulse Y: zero-crossing time. 53 Figure 4.10　 Impulse response of the LC tank in different time. 54 Figure 4.11　 Output waveform (left) and ISF (right). 55 Figure 4.12　 Evolution of circuit noise into phase noise. 57 Figure 4.13　 Design flow of the NMOS-only cross-coupled LC VCO. 59 Figure 4.14　 The 1-Volt NMOS-only cross-coupled LC VCO. 60 Figure 4.15　 Output swing of the 1-Volt NMOS-only cross-coupled LC VCO. 61 Figure 4.16　 Tuning range of the 1-Volt NMOS-only cross-coupled LC VCO. 61 Figure 4.17　 Phase noise of the 1-Volt NMOS-only cross-coupled LC VCO. 62 Figure 4.18　 Different corner of the 1-Volt NMOS-only cross-coupled LC VCO. 62 Figure 4.19　 Layout of the 1-Volt NMOS-only cross-coupled LC VCO. 62 Figure 4.20　 Die photo of the 1-Volt NMOS-only cross-coupled LC VCO. 63 Figure 4.21　 Control voltage measurement of the 1-Volt NMOS-only cross-coupled LC VCO. 63 Figure 4.22　 Phase Noise measurement of the 1-Volt NMOS-only cross-coupled LC VCO. 64 Chapter 5 Figure 5.1　　Characteristic of an ideal phase detector. 66 Figure 5.2　　PFD response with (a) A lagging B, and (b) ωA >ωB. 67 Figure 5.3　　(a) Block diagram of PFD with charge pump and (b) timing diagram. 67 Figure 5.4　　PLL based frequency synthesizer linear model. 68 Figure 5.5　　Loop Filter (a) first order, (b) Second order and (c) Third order. 69 Figure 5.6　　Block diagram of the frequency divider. 70 Figure 5.7　　Timing diagram of the frequency divider. 72 Figure 5.8　　The corresponding open-loop response of first-order loop filter. 72 Figure 5.9　　(a)First-order loop filter and (b) input and output signals. 74 Figure 5.10　 Granular transient response of a PLL with first-order loop filter. 74 Figure 5.11　 The corresponding open-loop response of second-order loop filter. 75 Figure 5.12　 Frequency domain representation of spurs. 78 Figure 5.13　 PLL noise transfer function from input to output. 80 Figure 5.14　 PLL noise transfer function from VCO to output. 82 Figure 5.15　 Block diagram of a frequency synthesizer. 82 Figure 5.16　 Block diagram of a PFD. 83 Figure 5.17　 Phase frequency detector (PFD). 84 Figure 5.18　 Characteristic curve of the phase detector and jitter in the time domain. 84 Figure 5.19　 Cell of the charge pump. 85 Figure 5.20　 Charge Pump with exclusion OR function. 86 Figure 5.21　 (a)Adaptive bandwidth controller (b) control signal generator. 86 Figure 5.22　 Block diagram of the divide-by-2/3 dual-modulus prescaler. 87 Figure 5.23　 Timing diagram of the divide-by-2/3 dual-modulus prescaler. 87 Figure 5.24　 TSPC DFF. 88 Figure 5.25　 (a)Type I, (b)type II and (c)IE-TSPC DFF. 89 Figure 5.26　 The voltage waveform of the E-TSPC and IE-TSPC. 90 Figure 5.27　 Circuit implementation of the divide-by-2/3 dual-modulus prescaler. 90 Figure 5.28　 Circuit schematic of the preamplifier. 91 Figure 5.29　 Closed loop simulation of the frequency synthesizer. 91 Figure 5.30　 Layout of the frequency synthesizer. 92 List of Tables Chapter 1 Chapter 2 Table 2.1 Receiver performance requirements. 15 Chapter 3 Chapter 4 Table 4.1 Predicted performances of the 1-Volt NMOS-only cross-coupled LC VCO. 61 Chapter 5 Table 5.1 Relationship between γ and PM. 77 Table 5.2 Summary of the frequency synthesizer. 92 Chapter 63175808 bytesapplication/pdfen-US低雜訊放大器無線區網頻率合成器壓控振盪器Frequency SynthesizerVCOLNAWLAN 802.11athesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/57344/1/ntu-93-R91943047-1.pdf