Tu, S.-W.S.-W.TuJou, J.-Y.J.-Y.JouYAO-WEN CHANG2018-09-102018-09-102004http://www.scopus.com/inward/record.url?eid=2-s2.0-2442531922&partnerID=MN8TOARShttp://scholars.lib.ntu.edu.tw/handle/123456789/309297Layout techniques for on-chip interconnect inductance reductionconference paper2-s2.0-2442531922