林宗賢Lin, Tsung-Hsien臺灣大學:電子工程學研究所方語賢Fang, Yu-HsienYu-HsienFang2010-07-142018-07-102010-07-142018-07-102009U0001-1108200918390600http://ntur.lib.ntu.edu.tw//handle/246246/189168本論文之主要研究為可操作於一伏特之兩百億赫茲的鎖相迴路設計，並且提出一個具有交叉耦合電容之電感電容式壓控震盪器。此壓控震盪器利用其與交叉耦合對之輸入寄生電容串聯之結構，使輸出震盪頻率大約提升了約1-GHz之多；此外，此壓控震盪器使用雙端差動、結構對稱且具有高品質因素之電感，並且降低交叉耦合對之等效轉導值，因此達到了相位雜訊在1-MHz位移頻率時為－106 dBc/Hz之效能，而此時之功率消耗為1-mW。另外一個在鎖相迴路中扮演關鍵性的電路區塊係非除頻器莫屬，面對20-GHz如此高之輸入頻率，第一、二級除頻器乃採用注入鎖定式之除頻器，藉由選擇適當之負載電感，前兩級注入鎖定式除頻器皆操作於合理之中心頻率，但為了能確保除頻器可以正確除頻，因此，可除頻範圍變成高速除頻器之最重要的設計指標，本論文亦提供一個快速且略為精確之可除頻範圍評估，以增加注入鎖定式除頻器之設計效率。本研究中，在注入鎖定式除頻器之後，使用電流模式邏輯之除頻器當做第三?六級之除頻器，達到其寬的可除頻範圍之特性，佈局後之模擬結果顯示出可除頻範圍為1.2?7.3-GHz，因此此除頻器可以在可能發生的PVT偏移之下正常操作。實際電晶體層與全波電磁分析之共同模擬結果顯示此鎖相迴路鎖定在20.6-GHz，並且在1-MHz之迴路頻寬、參考頻率為160.93-MHz之條件下，達到了－46.6 dBc的參考突波，此時，整個鎖相迴路之功率消耗為18.5-mW。In this work, a 20-GHz PLL with a 1-V supply is designed, where a pair of cross-coupled capacitors, Cf, is proposed and added to the LC-VCO. The two capacitors are inserted between the output and the gate of cross-coupled pair in the LC-VCO, and therefore lower the equivalent capacitance at output while looking into the series connection of Cf and the gate capacitance of cross-coupled pair. The LC-VCO uses this configuration, and therefore makes the output oscillation frequency raised by 1.0 GHz approximately. Besides, the LC-VCO employing a differential, geometrically symmetrical with high Q inductor and lowering the transconductance of cross-coupled pair accomplishes a phase noise of －106-dBc/Hz at 1-MHz offset with a minimum power of 1-mW.requency divider plays an essential role in a PLL system. In divider chain, the injection-locked frequency dividers are employed in the first and the second stage dividers. By selecting an adequate load inductor, the first and the second injection-locked frequency dividers operate at desired center frequency accordingly. Whereas, in order to ensure the frequency dividers can functionally work, a parameter, locking range, therefore becomes the most important design target especially for high-speed frequency dividers applications. This thesis provides a rapid and roughly accurate estimation of divider locking range, so as to increase design efficiency in injection-locked frequency dividers.n the divider chain of this work, current-mode logic based frequency dividers are adopted in four-stage cascaded-dividers after two-cascaded-stage injection-locked frequency dividers, arriving at a wide-locking-range characteristic. According to the post-layout simulations of the third to the seventh stages frequency dividers, they achieve a 1.2 to 7.3-GHz locking range wide. This result demonstrates the third to seventh stage frequency dividers can correctly operate under possible PVT variations.he transistor-level and 2.5-D EM co-simulation results of the PLL reveal that the PLL is locked at 20.6 GHz, and it achieves a magnitude of －46.6-dBc reference spurs with a 1-MHz loop bandwidth and a 160.93-MHz reference frequency, while consuming 18.5 mW from a 1-V supply.Contentsbstract vontents viiist of Figures ixist of Tables xiiihapter 1 Introduction 1.1 Motivation 1.2 Contributions of this Thesis 2.3 Organization of this Thesis 3hapter 2 Introductions to Phase-Locked Loop 5.1 Phase-Locked Loop Fundamentals 5.2 Basics of PLL Building Blocks 6.2.1 PFD, CP, and Loop Filter 7.2.2 Voltage-Controlled Oscillator 10.2.3 Frequency Divider 12.2.4 Analysis of PLL Loop Parameters 14.2.4.1 Second-order, Type-2 PLL 14.2.4.2 Third-order, Type-2 PLL 17.3 Phase Noise 19.4 Summary 21hapter 3 A 1-V 20-GHz Phase-Locked Loop in 0.18-mm CMOS 23.1 Challenges for Low-Voltage Operation 23.2 Method of Reducing Power 25.3 Circuit Implementation 27.3.1 Architecture 28.3.2 Phase Frequency Detector and Charge Pump 28.3.3 Loop Filter 30.3.4 Voltage-Controlled Oscillator 31.3.5 Frequency Divider 45.3.5.1 Static CML Frequency Divider 45.3.5.2 Injection-Locked Frequency Divider 55.4 Simulation Results 64hapter 4 Experimental Results 67.1 Testing Environment Setup 67.2 Printed Circuit Board Design 68.2.1 Chip Pin Configurations and PCB Design 68.2.2 Voltage Supply Generator 71.3 Experimental Results 72hapter 5 Conclusions and Future Work 73.1 Research Summary 73.2 Future Work/Improvement 74ibliography 75ist of Figuresig. 1 1 Block diagram of an optical transceiver 2ig. 2 1 Typical PLL building blocks 5ig. 2 2 Linear phase-domain model of a typical PLL 6ig. 2 3 (a) D flip-flop based PFD, (b) two possible timing diagrams 8ig. 2 4 PFD transfer characteristic 8ig. 2 5 PFD with charge pump 9ig. 2 6 (a) Non-idealities due to small phase difference, (b) Dead zone 10ig. 2 7 (a) VCO symbol, (b) VCO gain 11ig. 2 8 Trade-off between the phase noise and the KVCO 12ig. 2 9 Change the divide ratio by channel selection 13ig. 2 10 (a) First order loop filter, (b) bode plot of a second-order open loop PLL, (c) abrupt voltage drop on the VCO control voltage 15ig. 2 11 (a) Second order loop filter, (b) bode plot of a third-order open loop PLL, (c) improvement in abrupt voltage drop on the VCO control voltage 17ig. 2 12 (a) Ideal signals, (b) real signals 20ig. 3 1 Effect of forward-body biasing 24ig. 3 2 Comparisons of capacitors between small and large magnitude input 26ig. 3 3 Cross section of MOSFET (a) triode region, (b) saturation region 26ig. 3 4 A 1-V 20-GHz PLL Architecture 28ig. 3 5 All NAND gates PFD with additional delay stage 29ig. 3 6 (a) Simplified charge pump, (b) detailed charge pump implementation 30ig. 3 7 A 2nd order passive loop filter 31ig. 3 8 A typical feedback system 32ig. 3 9 The quality factor of the differential inductor 34ig. 3 10 NMOS capacitor of (a) accumulation, (b) depletion, (c) inversion mode 35ig. 3 11 MOS varactor structures and C-V curves 36ig. 3 12 Proposed LC-VCO (a) Complete schematic, (b) tuning curves of the VCO with and without DC bias scheme 38ig. 3 13 LC-VCO small signal model with varactors and inductor neglected 39ig. 3 14 Effect of ground-coupled noise (a) With tail current source, (b) without tail current source 40ig. 3 15 Equivalent model with varactors neglected 41ig. 3 16 Simulated tuning curves of the proposed LC-VCO with and without Cf 42ig. 3 17 LC-VCO noise analysis with half circuit only 43ig. 3 18 Phase noise optimization 44ig. 3 19 Static CML frequency divider model 46ig. 3 20 (a) A typical D Flip-Flop divider, (b) divide-by-2 waveform 47ig. 3 21 Equivalent model of a static CML frequency divider 47ig. 3 22 Operational range of the static CML frequency divider 49ig. 3 23 Schematic of CML latches (a) With current source, (b) without current source 50ig. 3 24 A master-slave D flip-flop 51ig. 3 25 (a) Static CML frequency divider, (b) its locking range 52ig. 3 26 Simulated locking range of the static CML frequency divider with 6 extreme corners 53ig. 3 27 Layout of static CML frequency dividers 54ig. 3 28 Post-layout simulations of the 3rd-6th frequency dividers 55ig. 3 29 LC-tank frequency divider generic topology 56ig. 3 30 Behavior model of the injection-locked frequency divider 56ig. 3 31 Phase response of a frequency divider with a dc and a sinusoidal input current 57ig. 3 32 (a) Schematic of the injection-locked frequency divider, (b) LO port feedback frequency divider 60ig. 3 33 Timing diagram of the injection-locked frequency divider 60ig. 3 34 Simulated locking range of the (a) 1st injection-locked frequency divider, (b) 2nd injection-locked frequency divider 62ig. 3 35 Locking process of the 1-V 20-GHz PLL 65ig. 3 36 Output spectrum of the PLL 65ig. 4 1 Measurement environment 67ig. 4 2 Pin configurations and power domain definition, (b) Die photograph with total size 69ig. 4 3 (a) Signal board view, (b) DC board view 70ig. 4 4 The low-dropout (LT3020) regulator schematic 71ist of Tablesable. 3 1 Loop filter design parameters 31able. 3 2 Performance comparison between three high-speed topologies 63able. 3 3 1-V 20-GHz PLL design parameters 64able. 3 4 Performance summary comparisons 662827015 bytesapplication/pdfen-US鎖相迴路壓控震盪器米勒除頻器除頻器參考突波低電壓Phase-locked loop (PLL)voltage-controlled oscillator (VCO)Miller dividerfrequency dividerreference spurslow-voltagethesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/189168/1/ntu-98-R95943035-1.pdf