Chen, Chi-MaoChi-MaoChenLin, Chih-HsiangChih-HsiangLinPEI YUN TSAI2024-09-182024-09-182015https://www.scopus.com/record/display.uri?eid=2-s2.0-84946238212&origin=resultslisthttps://scholars.lib.ntu.edu.tw/handle/123456789/721413Lisbon, 24 May 2015 through 27 May 2015This paper presents a configurable multi-mode QR decomposition (QRD) processor. It supports 4×4 and 8×8 QRD with multi-layer sorting for single-user MIMO precoding. Besides, it can perform block-based sorting for multi-user MIMO precoding. Both forward mode for decomposition and backward mode for signal precoding are provided. This QRD processor is designed in pipelined systolic array. An in-place strategy with pointer-based control mechanism is proposed for sorting buffers, which reduces 42.3% D flip-flops. The proposed processor implemented in 90nm CMOS technology can generate 9.45MQRD/s for decomposing 8×8 channel matrix with sorting, and outperforms the related works in terms of throughput and hardware efficiency. © 2015 IEEE.MIMO precodingmulti-user MIMOQR decompositionsortingsystolic arrayconference paper10.1109/ISCAS.2015.71693132-s2.0-84946238212