國立臺灣大學電機工程學系暨研究所闕志達2006-07-252018-07-062006-07-252018-07-062000-07-31http://ntur.lib.ntu.edu.tw//handle/246246/7788本計劃目的在建立一適用於基頻 訊號處理單元及資料路徑模組設計之 參數化模組設計架構。該架構由C++ 硬體類別﹑C++參數化模組庫與晶胞庫 構成。此架構下設計者指定系統參數 後，利用參數化模組可自動產生C++ 功能階層模擬程式碼與供晶片實體設 計閘之階層Verilog 硬體描述。藉此設 計流程我們可達到高設計抽象度及重 複使用率，較短之設計時間並避免設 計人員分別撰寫兩系統描述時可能發 生的錯誤。本計劃第一年中我們工作 在利用TSMC 0.6／0.35mm 兩製程設 計與測試晶胞庫，並提出參數化模組 之C++類別之雛型，利用晶胞庫試作 底層之參數畫模組。第二年中我們設 計較複雜及多樣化參數化模組，修改 原C++參數化模組類別及設計流程以 提昇功能階層模擬之效率，以及將參 數化模組庫與視窗圖形式程式設計環 境結合，讓設計者使用更加便利。The main objective of the project is to developing a parametric module design framework that is suitable for designing the baseband signal processing/datapath units. The framework is composed of C++ hardware related data classes, parametric module libraries and the cell libraries. In this framework, designers specify the system parameters and use the module generators to generate the C++ function simulating code and gate-level Verilog code used for physical design. The design flow achieves high-level abstraction and high reusability, short design time, and less prone to human errors. In the first year we focused on the design and verification of the cell libraries using TSMC 0.6/0.35mm technologies. Moreover, we proposed a C++ parametric module class, and use the class to design several simple modules. In the second year we try to design more modules, provide module with a variety of architectures, refine the hardware data classes to increase the efficiency of function simulation, and slightly modify the design framework. On the other hand, we integrate the module libraries into conventional C/C++ window-based programming environments to provide a friendly user interface and better class encapsulation.application/pdf451501 bytesapplication/pdfzh-TW國立臺灣大學電機工程學系暨研究所模組庫晶胞庫參數化模組module librarycell libraryparametric modulereporthttp://ntur.lib.ntu.edu.tw/bitstream/246246/7788/1/892215E002029.pdf