劉致為臺灣大學：電機工程學研究所賴文正Lai, Wen-ZhengWen-ZhengLai2007-11-262018-07-062007-11-262018-07-062004http://ntur.lib.ntu.edu.tw//handle/246246/53314隨著製程技術的進步，對於氧化層的各種不同特性要求也越嚴苛。當氧化層變得越薄，在反轉層時，原本只受電場加速的載子不再被我們的絕緣層阻擋住而直接穿透過去，因此形成相當大的穿隧電流。在做成元件之後，便無法達到低必v消耗的要求。本論文中，就是以原子層化學汽相沉積的高介電係數的材料來取代二氧化矽。利用高介電係數的材料作為絕緣層時，就能以更大的厚度降低載子直接穿透的機率，而使大部份的電荷維持在表層。 因為在原子層化學汽相沉積的成長過程中，會殘留水汽在我們使用的高介電係數的材料，並且因過度的氯氣而在介電層中產生缺陷。所以在成長完成之後，我們會針對這個問題用快速退火的方式解決，以免影響到元件本身的電性。藉由穿透式電子顯微鏡觀察到，預先以化學反應成長的二氧化矽阻擋層，在經過更高溫度，更長時間的退火處理，有繼續增加的趨勢。可以得知，外界多餘的氧仍能在高溫的情況下，鑽過絕緣層，和底部的矽反應形成二氧化矽。所以目前我們所能達到的等效二氧化矽絕緣層厚度大約為1.5個奈米。 然而，在我們使用的高介電係數的材料在以600度以上的高溫處理過後，不只厚度變高，並且會形成以多晶體的狀態存在。由於多晶體彼此互相連接的結晶邊界變得更多，使得載子能經由這些結晶邊界產生路徑，穿越絕緣層，形成更大的電流.。 另一方面，本材料直接和矽接合時，產生的界面缺陷,比二氧化矽更為嚴重。如何解決這些問題，便是我們當前努力的目標.。The various electrical and material properties of dielectrics are even more important along with the progress of our process technology. When thickness of oxide becomes very thin, carriers which can only be accelerated by electric field in inversion are no longer confined by the insulator and they will easily penetrate through the insulator to form a large number of leakage currents. The goal to low power consumption couldn’t be achieved and those devices are barely adopted. In this thesis, the alternative high-k dielectrics made by atomic layer chemical vapor deposition are used to instead of silicon dioxide. Therefore, the probability of carries directly penetrating through the insulator will be reduced with thick high-k film, and then charges can be kept in surfaces. The residual water was left in those deposited films and defects within insulators were formed due to overall chlorine during the process of atomic layer deposition. The problems could be eliminated by rapid thermal annealing after the deposition in order to enhance the good electrical characteristics of those films. According to the photography from transmission electron microscopy, we find that the intentionally grown chemical oxide became thicker after high temperature and long time annealing. It shown that the residual oxygen in the chamber penetrated through the high-k film and reacted with silicon to form silicon dioxide. The best we can do so far is to deposit high-k film with EOT below 1.5nm. However, all the high-k films were all crystallized after annealing at 600OC. This resulted in the increase of leakage currents. On the other hand, the interface trap charges with high-k dielectrics are larger than those with silicon dioxide. We will do our best to solve these problems.Contents Figure Captions Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Thesis Outline 2 Chapter 2 The Characteristic High-k Dielectrics 4 2.1 Characteristics of Hafnium Oxide 4 2.2 Thermal Stability and Dielectric Constant of High-k Films 5 2.3 Tunneling Current Increases Exponentially with Decreasing Oxide Thickness 9 2.4 Interface Reactions 11 2.5 Crystallization Temperature of HfO2 14 2.6 Transition Layer 17 2.7 Accurate Circuit Model 18 Chapter 3 Device Fabrication and Experiment Procedure 22 Chapter 4 Experiment Results and Discussions 24 4.1 The Characteristic and Electrical Properties of a 2nm HfO2 thin film 24 4.2 The Characteristic and Electrical Properties of a 5nm HfO2 thin film 25 4.3 The Characteristic and Electrical Properties of 3nm HfO2 thin films deposed on p-Si and Strain Si0.8Ge0.2 wafer 25 Chapter 5 High-k LED 48 5.1 Light Emission from Al/HfO2/Silicon Diodes 48 5.2 Device Fabrication and Experimental Procedure 49 5.3 Experiment Results and Discussions 50 5.4 Summary 52 Chapter 6 Conclusion and Future work 58 6.1 Conclusion 58 6.2 Future Work 59 Figure Captions Fig.2.1 Optical energy bandgaps vs. high-k gate dielectric constants. The bandgap of HfO2 is 5.6 eV. 7 Fig.2.2 Band alignment of high-k materials related to silicon substrate. 8 Fig.2.3 Simulated (solid lines) and Measurement (dots) tunneling currents in thin-oxide polysilicon-gate MOS devices. The dash line indicates a tunneling current level of A/cm2. 9-10 Fig.2.4 Carriers will direct penetrate through insulator with ultra thin gate dielectric physical thickness. 10 Fig.2.5 Interface reactions: structure and phase, kinetics/ thermodynamics mixing / segregation, amorphous/crystalline, growth/reduction. 12 Fig.2.6 Interface barrier layer for metal oxide in order to avoid interface reactions and metal silicate formation. 13 Fig.2.7 Three kinds of gate dielectric films were prepared by reactive sputtering: (a) reference HfO2 film by reoxidation method (control); (b) HfO2 deposited after substrate nitridation (bottom nitridation [BN]); (c) HfO2 with top nitrided layer (TN), but (d) the CVD HfOxNy film. 13 Fig2.8 XRD of HfO2 which were deposited by jet vapor deposition at room temperature on silicon substrate after various PDA temperatures. 15 Fig.2.9 Gate leakage currents of HfO2, HfAlO with ~ 6.8% of Al and HfAlO with ~ 31.7% of Al, as function of PDA temperature. 16 Figure.2.10 Equivalent small-signal circuit models of MIS capacitor: (a) Parallel circuit model for high-tunneling current and low serial resistance devices (b) Serial circuit model for low-tunneling current devices (c) Accurate circuit model 19-20 Fig.3.1 The cross section structure of Metal-insulator-semiconductor (MIS) device. 23 Fig.4.1 C-V curves of a 2nm HfO2 film made by ALCVD on p-type Si wafer and subsequently annealed in N2 at 600OC for 1 min with different frequencies: (a) Before post metallization anneal.(b) After post metallization anneal in forming gas (N2:90%+H2:10%) at 400OC for 30 min. 30 Fig.4.2 J-V curves of a 2nm HfO2 film made by ALCVD on p-type Si substrate and subsequently annealed in N2 at 600OC for 1 min. 31 Fig.4.3 Cross-section TEM micrograph of 2nm HfO2 made by ALCVD on p-type Si wafer, after 1 min post deposition anneal in N2 at 600 ℃ (a) Before post metallization anneal. (b) After post metallization anneal in forming gas (N2:90%+H2:10%) at 400OC for 30 min. 32 Fig.4.4 C-V curves of a 5nm HfO2 film made by ALCVD on p-type Si wafer and subsequently annealed in N2 at 600OC for 1 min with different frequencies: (a) Without post metallization anneal. (b) After post metallization anneal in forming gas (N2:90%+H2:10%) at 400OC for 30 min. 33 Fig.4.5 Cross-section TEM micrograph of 5nm HfO2 made by ALCVD on p-type Si wafer with post deposition anneal in N2 at 600 ℃ for 1min and post metallization anneal in forming gas at 400 ℃ for 30min. 34 Fig.4.6 C-V curve sof a 3nm HfO2 film with PDA temperature 600OC and PMA with different frequencies. (a) HfO2 on Si substrate. (b) HfO2 on Si0.8Ge0.2 substrate. 35 Fig.4.7 C-V curves of a 3nm HfO2 film with PDA temperature 700OC and PMA with different frequencies. (a) HfO2 on Si substrate. (b) HfO2 on Si0.8Ge0.2 substrate. 36 Fig.4.8 C-V curves of a 3nm HfO2 film with PDA temperature 800OC and PMA with different frequencies. (a) HfO2 on Si substrate. (b) HfO2 on Si0.8Ge0.2 substrate. 37 Fig.4.9 C-V curves of 3nm HfO2 film annealed at PDA temperature 900OC and PMA with different frequencies. (a) HfO2 on Si substrate. (b) HfO2 on Si0.8Ge0.2 substrate. 38 Fig.4.10 J-V curves of 3nm HfO2 films made by ALCVD on p-type Si wafer and subsequently annealed in N2 at PDA temperature 600OC, 700OC, 800OC and 900OC for 5 min. 39 Fig.4.11 J-V curves of 3nm HfO2 films made by ALCVD on Si0.8Ge0.2 wafer and subsequently annealed in N2 at PDA temperature 600OC, 700OC, 800OC and 900OC for 5 min. 40 Fig.4.12 Gate leakage currents changed with PDA temperature from Pt/HfO2/Si and Pt/HfO2/Si0.8Ge0.2 MIS Structures. 41 Fig.4.13. Effective oxide thickness is function of PDA temperature. 42 Fig.4.14 Cross-section TEM micrograph of a 3nm HfO2 film made by ALCVD on p-type Si wafer with post deposition anneal in N2 at 600 ℃ for 5min. 43 Fig.4.15 Cross-section TEM micrograph of a 3nm HfO2 film made by ALCVD on p-type Si wafer with post deposition anneal in N2 at 900 ℃ for 5min. 44 Fig.4.16 Cross-section TEM micrograph of a 3nm HfO2 film made by ALCVD on strain Si0.8Ge0.2 wafer with post deposition anneal in N2 at 600 ℃ for 5min.45 Fig.4.17 Cross-section TEM micrograph of a 3nm HfO2 film made by ALCVD on strain Si0.8Ge0.2 wafer with post deposition anneal in N2 at 900 ℃ for 5min. 46 Fig.5.1 Cross-section TEM micrograph of HfO2 on p-type Si wafer, after 1 min post deposition annealing at 600 ℃. 53 Fig.5.2 The measured electroluminescence spectra of HfO2 LED with the fitting curves by the electron-hole plasma recombination model. The inset shows the external quantum efficiency of the HfO2 and SiO2 devices. 54 Fig.5.3 A schematic energy band diagram of a MIS diode on p-type Si wafer at accumulation bias. The dash line and solid line represent the band alignments of HfO2 and SiO2 devices, respectively. The inset is the electric field at different gate bias by numerical simulation. 55 Fig.5.4 The electroluminescence spectrum of HfO2 LED with a long tail at the energy lower than the Si bandgap at room temperature. The inset is integrated intensity ratio vs. gate current density 56 Fig.5.5 The comparison of the normalized electroluminescence spectra of the HfO2 and SiO2 LEDs. 57 Table Captions Table 1 Elements that have an oxide that is thermodynamically stable in contact with silicon. 6 Table 2 Dielectric constants of some popular gate dielectric materials. 8 Table 3 Recipes of samples prepared for experiment. 23 Table 4 Electrical properties of Pt/HfO2/p-Si MIS device related to PDA temperature. *: Unknown physical thickness of a nominal 3.0nm HfO2 film. 47 Table 5 Electrical properties of Pt/HfO2/Si0.8Ge0.2 MIS device related to PDA temperature. *: Unknown physical thickness of a nominal 3.0nm HfO2 film. 471777729 bytesapplication/pdfen-US高介電係數閘極絕緣體kHighInsulatorGatethesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/53314/1/ntu-93-R89921077-1.pdf