盧奕璋Lu, Yi-Chang臺灣大學:電子工程學研究所陳晉凱Tang, Chin-KhaiChin-KhaiTang2010-07-142018-07-102010-07-142018-07-102009U0001-2107200913250300http://ntur.lib.ntu.edu.tw//handle/246246/189161In this thesis, a new asynchronous circuit design is presented. Its fine-grained architecture design in circuit block has enabled faster and more efficient self-timed operation, which could achieve higher frequency than other asynchronous circuit design styles. A special technique that enables faster forwarding is also applied, and the forward transition of data token is shortened. The new asynchronous circuit design style is applied to implement self-timed parallel tree fast adders, and the performance is compared to those of static logic and dynamic logic circuits.he new asynchronous circuits are constructed with strong indicatability NMOS pull-down network so that the circuit architecture is simple and faster. More efficient signal generation for restoring the channels and circuit nodes is designed to lower the total transistor area and to improve frequency of operation. The handshaking process and the cycle time of the asynchronous circuits are analyzed, and its performance and functionality under fabrication and temperature variations are evaluated through Monte Carlo simulations in 180nm and 65nm technology nodes. The proposed new asynchronous circuits are compared to the static and domino logic circuits to assess their delay variations and functional success rates under different frequencies and temperatures of operation.Acknowledgements ---------------------------------------------------------------------------------- ibstracts ---------------------------------------------------------------------------------------------- iiiist of Figures ---------------------------------------------------------------------------------------- vi Introduction -------------------------------------------------------------------------------------- 1.1 The Digital Synchronous VLSI Circuits.--------------------------------------------- 2.2 Process Variations.---------------------------------------------------------------------- 3.3 Applications of Asynchronous Circuits.---------------------------------------------- 4.4 Chapter Summary.----------------------------------------------------------------------- 5 Fundamentals of Asynchronous Circuit Design.------------------------------------------- 7.1 Bundled-Data Protocols.--------------------------------------------------------------- 8.1.1 Introduction.------------------------------------------------------------------------ 8.1.2 4-Phase Bundled-Data Protocol.------------------------------------------------- 9.1.3 2-Phase Bundled-Data Protocol.------------------------------------------------- 10.2 4-Phases Dual-Rail Protocol.---------------------------------------------------------- 11.2.1 Introduction.------------------------------------------------------------------------ 11.2.2 Single-Track Full-Buffer Design.------------------------------------------------ 13.3 Chapter Summary.----------------------------------------------------------------------- 17 Single-Rail Asynchronous Processing Unit.------------------------------------------------ 18.1 Basic Action Flow.---------------------------------------------------------------------- 19.2 Asynchronous Circuit with Efficient Restoring Path.------------------------------ 20.2.1 Circuit Design Introduction.------------------------------------------------------ 20.2.2 Circuit Reset.----------------------------------------------------------------------- 21.2.3 Circuit Operation.------------------------------------------------------------------ 22.3 Chapter Summary.----------------------------------------------------------------------- 26 1-out-of-2 Encoding Dual-Rail Asynchronous Functional Units.----------------------- 27.1 1-out-of-2 Encoding.-------------------------------------------------------------------- 28.2 Strong Indicatability.-------------------------------------------------------------------- 28.3 1-out-of-2 Encoding Asynchronous Functional Unit.------------------------------ 29.3.1 Basic Architecture.----------------------------------------------------------------- 29.3.2 Asynchronous AND Circuit.----------------------------------------------------- 32.3.3 Asynchronous OR Circuit.-------------------------------------------------------- 34.3.4 Asynchronous XOR Circuit.------------------------------------------------------ 36.3.5 Asynchronous Generate Circuit.------------------------------------------------- 38.4 Power Consumption.-------------------------------------------------------------------- 40.5 Chapter Summary.----------------------------------------------------------------------- 42 Asynchronous Buffer Circuit with Fast Forwarding Technique.------------------------- 43.1 Asynchronous Buffer Circuit.--------------------------------------------------------- 44.1.1 Circuit Design.---------------------------------------------------------------------- 44.1.2 Circuit Operation.------------------------------------------------------------------ 45.2 Asynchronous Fork Unit.--------------------------------------------------------------- 51.3 Chapter Summary.----------------------------------------------------------------------- 53 Simulation and Comparison Results.-------------------------------------------------------- 54.1 Comparisons of Frequency in Different Temperatures.---------------------------- 55.2 Chapter Summary.----------------------------------------------------------------------- 58 Conclusions.------------------------------------------------------------------------------------- 59 References.-------------------------------------------------------------------------------------- 61690290 bytesapplication/pdfen-US快速前傳技術非同步電路設計Fast forwardingAsynchronous Circuit Designthesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/189161/1/ntu-98-R95922172-1.pdf