Chi-Nan ChuangSHEN-IUAN LIU2018-09-102018-09-102007-1115497747http://scholars.lib.ntu.edu.tw/handle/123456789/333724https://www.scopus.com/inward/record.uri?eid=2-s2.0-55649098872&doi=10.1109%2fTCSII.2007.904155&partnerID=40&md5=dbc8d531d8eff4cb470a20a1e7c289c7A 0.5-5 GHz wide-range multiphase delay-locked loop (MDLL) with a calibrated charge pump is presented. A multiperiod-locked technique is used to enhance the input frequency range of a MDLL and avoid the harmonic-locked problem. The charge pump current is also calibrated to reduce the static phase error. This MDLL has been fabricated in 0.13- CMOS process. The measured root-mean-square and peak-to-peak jitters are 1.06 and 8 ps at 5 GHz, respectively. The power dissipation at 5 GHz is 36 mW for a supply voltage of 1.2 V. © 2007 IEEE.Calibration; Charge pump; Delay-locked loop; Multiperiod-locked techniqueCalibration; Charge pump circuits; Charge pump; Charge pump currents; Delay-locked loops; Input frequency; Multi-period; Root Mean Square; Static phase errors; Supply voltages; Delay lock loopsjournal article10.1109/TCSII.2007.9041552-s2.0-55649098872WOS:000250992300003