陳中平臺灣大學：電子工程學研究所陳長宏Chen, Chang-HungChang-HungChen2007-11-272018-07-102007-11-272018-07-102005http://ntur.lib.ntu.edu.tw//handle/246246/57578本篇論文主旨在於實現適用於IEEE 802.11a無線區域網路系統的發射機電路，在論文中的電路設計分為兩大部分，包括了混波器(Mixer) 與功率放大器(Power Amplifier)，皆採用台積電標準點18微米1P6M互補式金氧半導體(CMOS)的製程來展現先進次微米製程的高效能表現並解決實現上所遭遇的問題。 第一部份是探討升頻轉換混波器的設計。吾人以Gilbert Cell架構為核心，採用完全差動正交的基頻輸入訊號電流直接升頻轉換至所需頻帶。由於直接升頻轉換(Direct-Conversion)架構內不需要中頻電路，直接將基頻(BB)訊號轉換至高頻(RF)訊號，如此可省略中頻電路之設計。儘管如此，由於發送訊號之頻率與本地振盪器之頻率相近，其發送訊號之大功率影響到混波器之本地振盪器訊號時所產生的Leakage 問題及Injection Pulling現象卻成為此一架構所需解決與克服的。相較於傳統的混波器架構，吾人提出電流回收(current-reuse)的電路技巧,配合Gilbert Cell與雙端平衡差動的架構,在轉移功率增益（conversion power gain）、雜訊指數(Noise figure)、隔絕度(isolation)與線性度(linearity)方面皆大幅提昇混波器的效能以期能符合IEEE 802.11a WLAN的規格。 第二部份是探討功率放大器的設計。吾人使用電容補償方式來增加CMOS功率放大器的線性度，使其適用於IEEE 802.11a無線區域網路的規格。電路設計功率輸出目標高達20dBm(100mW) ，採用TSMC提供之RF標準電晶體模型，完全使用0.18μm的最小通道長與薄氧化層(thin oxide)來實現。相較於傳統的CMOS功率放大器採用厚氧化層能有更高效能的表現，因採用厚氧化層電晶體則最小通道長為0.35μm。但先進次微米製程在高功率大電壓的輸出將面對到兩個很嚴重的問題：第一，將會使薄氧化層崩潰。第二是熱載子效應。另一方面來說，這也是影響電路產品的使用壽命與品質因素。所以本篇論文將對這兩個問題採用自我偏壓(self-biased) 方式來解決功率放大器的熱載子效應，同時避免採用厚氧化層電晶體來避開氧化層崩潰問題因而犧牲了次微米製程的高效能優點。 由於IEEE 802.11a系統的OFDM與64-QAM調變訊號要求線性度極高，本論文將採用NMOS二極體線性器電路來提高整體輸出的線性度，相較於其他線性化技巧，例如PMOS線性器。此法相對的不消耗電流，且可較傳統的電感偏壓節省相當多的晶片面積。此外，本設計加入了平行電感補償技術，吸收輸出端的雜散電容效應，使得功率放大器有更高增益的輸出表現。 本實驗室的研究著重於射頻前端(RF Front-End)電路的設計，且為因應SOC 的觀念，採用可與數位電路整合的CMOS製程為主。未來本發射機將可配合接收機(receiver)與頻率合成器(Frequency Synthesizer)電路以完成單一晶片(Single Chip)的802.11a收發機(transceiver)。The CMOS RF transmitter was implemented to meet the requirement of IEEE 802.11a Wireless LAN Systems are presented in this thesis. The circuit design in this thesis is divided into two main parts including mixer and power amplifier, and that all implemented with the process of TSMC 0.18um 1P6M CMOS to show the higher performance in deep sub-micro process and overcome the difficulties we met. The first main part is on the design of up conversion mixer. We based on the Gilbert Cell structure and used base-band input signal of fully differential quarter to direct up conversion. Since this architecture modulates signal without an IF section circuit, the low frequency (Base-band) signal is direct up conversion to high frequency (RF). So this architecture can omit the design of IF circuit. Even though, since the frequency of transmitter is close to local oscillator, The leakage problem and injection pulling phenomenon becomes the drawbacks of this architecture that we must solve and overcome. Compared with the conventional architectures of mixer, we presented the circuit technique of current reuse, combined with Gilbert cell and architecture of differential balance. After all, this improved mixer has better performance in conversion power gain, noise figure, isolation and linearity for applied in IEEE 802.11a WLAN standard. The second main part is on the design of power amplifier. We adopt the two stage cascade with capacitance compensation schemes to improve the power gain and linearity of CMOS power amplifier for WLAN applications of IEEE 802.11a. The output power in this circuit design is over 20dBm(100mW) and fabricated in a standard 0.18um single-poly-six-metal (1P6M) RF CMOS process of TSMC. Compared with the conventional CMOS PAs used the thick oxide devices, The improved circuit can have the higher performance since the minimum channel length of thick oxide devices is 0.35um. But there are two main issues in the design of power amplifier in submicron CMOS process, namely, oxide breakdown and hot carrier effect. On the other hand, are reliability and lifetime issues of the circuit products. So, in this thesis, the self-biased technique is presented that relaxes the restriction due to hot carrier degradation in power amplifier and alleviates the need to used thick-oxide transistors that have poor RF performance compared with the standard transistors available in the same process. Since the linearity requirement of the modulation signal in OFDM and 64-QAM for IEEE 802.11a is higher than the others, adopt the NMOS diode linearizer to improve the linearity in this design. Compared with the other linaer technique, for example, PMOS linearizer. There is no DC current consume in the improved method, and save much chip area compared with the conventional method of inductor biased. In addition, included the parallel inductor compensation technique to absorb the parasitical capacitance effect, makes the power amplifier have the higher performance in power gain. Our laboratory centred on the research of front-end circuit design. For the concept of SOC, we adopt the process of CMOS that can integrate with digital circuit. In the future, this transmitter will can complete in a signal chip of 802.11a transceiver with receiver and frequency synthesizer.第一章 簡介…………………………………………………………IX 第二章 發射器架構概論……………………………………………X 第三章 升頻轉換混波器之設計……………………………………XI 第四章 功率放大器之設……………………………………………XII 第五章 電路模擬、實作與量測……………………………………XIII 第六章 結論與未來工作……………………………………………XIV TABLE OF CONTENTS Abstract (Chinese) ………………………… I Abstract (English) ………………………… III Acknowledgement………………………… V Contents………………………… VI Table Captions ………………………… XVI Figure Captions ………………………… XVI * * CHAPTER 1 INTRODUCTION………………………… 1 1.1 IEEE 802.11a Specification Review………………………… 1 1.1.2 OFDM (used in 802.11a)..……………………………….... 1 1.1.3 Receiver and Transmitter Specification in 802.11a……..... 3 1.2 Design Background and Motivation…………………………. 4 1.3 Organization of This Thesis…………………………………. 6 CHAPTER 2 REVIEW OF TRANSMITTER ARCHITECTURESb 7 2.1 Direct-Conversion Transmitter Architecture………………… 8 2.1.1 Operation in a Direct-Conversion Transmitter……………. 8 2.1.2 Problem of Leakage……...………………………………... 9 2.1.3 Phenomenon of Injection Pulling…………………………. 10 2.1.4 Improvements……………………………………………... 11 2.2 Two-Step Transmitter Architecture …………………………. 12 2.2.1 Operation in a Two-Step Transmitter...…………………… 13 2.2.2 Choice of IF Frequency…………………………………… 14 2.3 Proposed System Architecture………………………………. 15 2.4 Basic Concepts in RF Design………………………………... 16 2.4.1 Conversion Gain…………………………………………... 16 2.4.2 1-dB Compression Point…………………………………... 17 2.4.3 Third-Order Interception Point……………………………. 18 2.4.4 Port Return Loss and Isolation….………………………… 22 2.4.5 Stability…………………………………………………… 23 CHAPTER 3 DESIGN OF A 5.25 GHz CMOS UP-CONVERSION MIXERbbbbbbbbbbb 25 3.1 Introduction to Mixer………………………………………... 25 XIV 3.1.1 General Considerations……...……………………………. 27 3.1.2 Port-to-Port Isolation……………………………………… 33 3.1.3 Mixer Topology…………………………………………… 33 3.1.3.1 Single-Balanced and Double-Balanced Mixer…………. 34 3.1.3.2 Passive Mixer…………………………………………... 36 3.1.3.3 Square-law Mixer………………………………………. 38 3.1.3.4 Active-Load Body-effect Mixer………………………... 39 3.2 Current-reuse bleeding Mixer……………………………….. 42 3.3 Circuit Design of Up-Conversion Mixer…………………….. 45 3.3.1 Core Circuit Design (Gilbert Cell Mixer)………………… 46 3.3.2 Core Circuit Design (Current-Reuse Bleeding Mixer)……. 50 3.3.3 Schematic Circuit of Up-Conversion Mixer………………. 51 3.4 Simulation Results of Up-Conversion Mixer ……………….. 53 3.4.1 Conversion Gain and 1-dB Compression Point…………… 54 3.4.2 Conversion Gain Versus LO Power………………………. 55 3.4.3 Third-Order Interception Point (IP3)……………………… 56 3.4.4 Port to Port Isolation………………………………………. 57 3.4.5 Single Sideband Noise Figure…………………………….. 58 3.4.6 Transient Simulation……………………………………… 60 3.4.7 Simulation Summary of Up-Conversion Mixer…………... 61 CHAPTER 4 DESIGN OF A 5.25 GHz CMOS POWER AMPLIFIER…………………………………... 62 4.1 Introduction to Power Amplifier…………………………….. 63 4.1.1 General Consideration…………………………………….. 64 4.1.2 Linear Power Amplifiers………………………………….. 64 4.2 Review on Power Amplifier Linearization Techniques……... 68 4.2.1 Feedback Techniques……………………………………... 68 4.2.1.1 Envelope Feedback……………………………………... 68 4.2.1.2 Cartesian Feedback……………………………………... 69 4.2.1.3 Polar Feedback…………………………………………. 70 4.2.2 Predistortion Techniques………………………………….. 71 4.2.2.1 Analog Predistorters……………………………………. 72 4.2.2.2 DSP Predistortion Techniques………………………….. 74 4.2.3 Envelope Elimination and Restoration……………………. 76 4.3 Design Concepts of CMOS Power Amplifiers……...……….. 78 4.4 Linearity Improvement Circuit Techniques…………………. 83 4.4.1 Nonlinear Capacitance Compensation Technique………… 84 4.4.1.1 PMOS capacitance compensation Technique………….. 89 4.4.1.2 NMOS diode linearizer Technique……………………... 90 4.4.2 Parallel Inductor Compensation Technique………………. 92 4.5 Self-biased and bootstrapping Technique…………………… 93 4.5.1 Convention Cascode Amplifier…………………………… 95 XV 4.5.2 Self-biased Cascode Amplifier……………………………. 97 4.5.3 Boost-trapped Cascode Amplifier………………………… 99 4.6 Circuit Realization…………………………………………… 101 4.6.1 Matching Network with Bond-wire and PAD…………….. 101 4.6.2 Schematic Circuit of Power Amplifier……………………. 103 4.7 Simulation Results of Power Amplifier.…………………….. 106 4.7.1 S-Parameter Simulation…………...………………………. 106 4.7.2 Stability Simulation………………..……………………… 108 4.7.3 1-dB Compression Point …..……………………..……… 109 4.7.4 Third-Order Interception Point (IP3)...……………………. 109 4.7.5 Power Gain and PAE………..…………………………….. 110 4.7.6 OFDM spectral flatness…………………………………… 111 4.7.7 Simulation Summary of Power Amplifier………………… 112 CHAPTER 5. Experimental Results ……………………………………… 115 5.1 Chip Layout Descriptions …………... ……………………… 115 5.2 Testing Environment ……………………………………… 118 5.3 Experimental Results………………………………………… 122 5.3.1 Measurement Results of NMOS diode Compensation PA... 125 CHAPTER 6 CONCLUSIONS AND FUTURE WORK………………… 136 6.1 Conclusions………………………………………………….. 136 6.2 Future Works………………………………………………… 137 References …………………………………………………………………………………………………………… 139 APPENDIX A POST-SIMULATION RESULTS11130255 bytesapplication/pdfen-US直接升頻轉換平行電感補償技術電流回收功率放大器混波器自我偏壓技術IEEE 802.11aNMOS二極體線性器NMOS diode linearizerself-biased techniquecurrent-reuseparallel inductor compensation techniquePower amplifierMixerDirect-up Conversionthesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/57578/1/ntu-94-R91943071-1.pdf