黃俊郎臺灣大學：電機工程學研究所胡凱舜Hu, Kai-ShunKai-ShunHu2007-11-262018-07-062007-11-262018-07-062007http://ntur.lib.ntu.edu.tw//handle/246246/52955平均與最高功率管理在現行掃描鏈測試中成為一個嚴重的議題，測試IC時會產生比一般工作情況下更大的功率消耗，本篇論文提出一個新的自動測試圖樣產生技術，目標在降低測試功率消耗，此技術同時考慮移入(shift)與捕捉(capture)時之平均與最高功率消耗。 此技術整合一功率限制之自動測試圖樣產生引擎，一功率限制之動態測試向量壓縮機制，一未指定值位元填充(X-filling)方法，與一重新安排測試向量順序方法，以達到降低功率之目的。此外，本論文提出一機制，將此降低測試功率技術與現行商業自動測試圖樣產生器連接，用以降低此降低測試功率技術所需之執行時間但仍保有相同之降低功率效能。此技術可應用在不同故障模型(fault model)與不同測試條件中，實驗中使用ISCAS89電路驗證此技術於不同故障模型中皆有效降低平均與最高功率消耗。Average and peak power management has become a serious challenge for scan-based testing. This thesis proposes a test pattern generation methodology that reduces the power dissipation during the shift and capture cycles of conventional scan testing. The proposed methodology utilizes a power-constrained ATPG engine and a dynamic compaction scheme to generate partially specified low power patterns. Then, X-filling together with test pattern ordering is employed to enhance the achievable power reduction. Besides, a mechanism of integration with commercial ATPG is proposed which iteratively replaces the high power consumption patterns with low power ones. Furthermore, the proposed low power test pattern generation methodology can be extent to various fault models, different test application scheme, and different test application conditions. The proposed technique is validated using ISCAS89 benchmark circuits.誌謝 i 中文摘要 ii Abstract iii Table of Contents iv List of Figures vi List of Tables viii Chapter 1 Introduction 1 Chapter 2 Preliminaries 3 2.1. Fault Models 3 2.2. Test Pattern Generation 4 2.3. Dynamic Test Pattern Compaction 5 2.4. Scan Test Application 6 2.5. Integrated at-speed ATPG Workflow 8 2.6. Power Dissipation Model 9 2.6.1. Dynamic Power Dissipation 9 2.6.2. Weighted Switching Activity 9 Chapter 3 A Study of Low Power Testing Methodologies 10 3.1. Introduction 10 3.2. General Considerations 10 3.2.1. Challenges in Low Power Testing 10 3.2.2. Fault Models 11 3.3. Prior Works in Low Power Testing 11 3.3.1. Circuit Modification Class 11 3.3.2. Test Pattern Generation and Post-processing Class 16 3.3.3. Hybrid Techniques 19 Chapter 4 Proposed Low Power Test Pattern Generation Methodology 20 4.1. Introduction 20 4.2. Test Power Estimation 21 4.3. Power Estimation of Partially Specified Test Patterns 21 4.4. Low Power Test Pattern Generation 25 4.4.1. Power Constrained Dynamic Compaction 26 4.4.2. Power Constrained ATPG Engine 27 4.5. Low Power X-Filling 28 4.6. Test Pattern Ordering 30 4.7. Extension to Handle Bridging Fault Model 33 4.8. Extension to the Broadside Scheme 33 4.9. Capture Power Dissipation 35 Chapter 5 Integration with Commercial ATPG 36 5.1. Motivation 36 5.2. Overview 36 5.3. Identify Bad Patterns 38 5.5. Target Fault Extraction 38 5.6. Low Power ATPG 39 5.7. Decision Making 39 Chapter 6 Experimental Results 41 6.1. Test vs. Functional Power Consumption 41 6.2. Effectiveness of Each Proposed Technique 42 6.3. Run Time Impact of Each Proposed Technique 44 6.4. Low Power Test Generation Results 46 6.4.1. Stuck-at Fault Model 46 6.4.2. Transition Fault Model 48 6.4.3. Path Delay Fault Model 51 6.4.4. Bridging Fault Model 53 6.4.5. Integrated at-speed ATPG Flow 55 6.5. The Mode of Focus on Capture/Shift Power Dissipation 57 6.6. Integration with Commercial ATPG 59 6.7. Compare with Other Works 61 Chapter 7 Conclusions 65 Bibliography 661664467 bytesapplication/pdfen-US掃描鏈功率自動測試圖樣產生scan chainlow powerATPGthesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/52955/1/ntu-96-R94921022-1.pdf