郭斯彥臺灣大學：電子工程學研究所尤建智Yu, Chien-ChihChien-ChihYu2007-11-272018-07-102007-11-272018-07-102004http://ntur.lib.ntu.edu.tw//handle/246246/57357在單晶片(SoC)整合的時代，電路設計的複雜程度隨著每單位面積可容納電晶體數目快速增加而增加。電路弁鉣褌狴堳e已經占不可重覆工程費用 (non-recurrent engineering) 相當重要的部份。目前針對系統單晶片的驗證環境還是有釵h的問題和盲點須待解決。傳統暫存器轉換層 (register transfer level)驗證流程佔據高達60%設計週期。如何在不大幅增加計算時間的前提上強化可測試弁鉦[輔v是一個巨大挑戰。另一個驗證工具需要去面對是如何將所有現有的軟硬體設計環境整合起來，並且可以在單一驗證平台中同時針對所有的軟硬體測試其正確性。 本論文將提出一個改良assertion為主的驗證系統，這個新的驗證系統不僅僅擁有傳統的一切驗證套件，更重要是這個驗證系統還涵辣棠曌h，和韌體曾所會執行的軟體。本驗證環境的核心是由一套匯流排弁鉏珩?(bus functional model)和規則驗證器，訊號記錄器，和存在去韌體層的軟體所共同組成。我們發展一套名為TestWizard的規則驗證套件來輔助整個系統。這個測試平台設計目標是以驗證所有PCI和PCI-Express弁鄔M匯流排行為為主並可針對單一元件或是系統效能做出重點評估。本驗證套件不僅可以驗證其電路設計的整合性，更可以透過效能評估系統幫助工程師來強化或針對其弱點進行改進。 實驗數據顯示待測電路跑完所有的測試項目後可以獲得很高的驗證涵輔v，而韌體層和規則驗證器之間的運作配X的非常良好。根據結果，可證明我們所提出的驗證套件是可行且非常有效的。Circuit design becomes more and more complicated in the system on chip (SoC) due to increasing capacity of integrating gates into one chip. Verification takes a major part of non-recurrent engineering (NRE) cost of entire design flow. Basically there are two major problems exist in current verification procedure. Traditional register transfer level (RTL) verification method could take about 60% work of design cycle. Another issue is how to integrate each component into a single environment and co-verify all devices simultaneously. This thesis describes a new verification environment with assertion-based technique and with firmware layer to provide a system level verification. Cores of this verification tool are bus functional models, bus protocol monitor, firmware layer software, and a set of assertion checkers called TestWizard. We developed a platform to verify the behavior of PCI and PCI-Express devices that can test all behaviors efficiently. A set of performance evaluation tools are be developed at the same time. By applying these performances tools, the verification environment helps designers not only to verify the correctness of circuit function, but can help hardware designer to evaluate the performance in a user-defined condition. From experimental results, the functional coverage for processing all compliance test scenarios in this verification environment is very high and firmware layer model work very well. The results also light the possibility of checking cross-protocol transaction. This verification system is proved to be effective and efficient in the real world.Chapter 1 Introduction 9 1.1 Challenge of Verification in SoC Era 9 1.2 Popular Verification Methodology 9 1.3 PCI/PCI-X and PCI-Express Architecture 10 1.4 Framework of PCI-Express and PCI/PCI-X Verification Environment 11 Chapter 2 12 Overview Assertion-Based Transaction Level Verification 12 2.1 Assertion-Based Verification 12 2.2 Concept of Transactional Level Verification 13 2.3 Bus Functional Model 15 Chapter 3 17 Assertion Checker-TestWizard 17 3.1 TestWizard 17 3.2 Record Class 19 3.2.1 Overview of Record Class 19 3.3 List Class 22 3.3.1 Overview of List Class 22 3.4 Temporal Assertion Function 24 3.4.1 Overview of Temporal Assertion 24 3.5 Transaction Logging Class 29 3.5.1 Overview of Transaction Logging 29 3.5.2 Transaction Logging Declaration and Elimination 30 3.5.3 Transaction Logging Access Methods 31 3.5.4 Transaction Logging Timing Method 31 3.6 Profile Class 32 3.6.1 Overview of Profile Class 32 3.6.2 Profile Control Function 33 3.6.3 Profile Update Function 34 Chapter 4 36 PCI/PCI-X and PCI-Express Architecture 36 4.1 PCI Local Bus Architecture 37 4.2 PCI-X Architecture 38 4.3 PCI-Express Architecture 40 4.3.1 Background of PCI-Express 40 4.3.2 PCI-Express Structure 40 Chapter 5 45 PCI/PCI-X/PCI-Express Verification System 45 5.1 Verification System Overview 45 5.2 PCI /PCI-X/PCI-Express Bus Functional Model 46 5.2.1 PCI and PCI-X Bus Function Model 46 5.2.2 PCI-Express Bus Function Model 48 5.3 Intel C++ PCI-Express Virtual Behavior Model 50 5.3.1 Intel Bus Function Model Architecture 50 5.3.2 Class Method 51 5.4 Virtual System Infrastructure 53 5.4.1 Enumeration Algorithm 54 5.5 Super Monitor 57 5.6 Functional Coverage 58 5.7 Compliance Test Suit 59 5.8 Experimental Results 60 5.9 Discussion 64 5.9.1 Power Management Procedure Dead Lock 65 5.9.2 Inefficient Transaction of Power Management 65 Chapter 6 Conclusion and Future Work 67 References 682383343 bytesapplication/pdfen-US驗證PCI-ExpressPCIverificationthesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/57357/1/ntu-93-R91943004-1.pdf