國立臺灣大學電子工程學研究所黃俊郎2006-08-232018-07-102006-08-232018-07-102003-11-30http://ntur.lib.ntu.edu.tw//handle/246246/29235由於時脈偏移(clock skew)的限制，並列通信(parallel communication)已經在資 料傳輸速度上遇到瓶頸，而正逐漸的被高時脈速度(clock rate)的串列通信(serial communication)所取代。以電腦週邊的聯結標準為例，USB 2.0、Firewire、Serial ATA 等標準皆為高時脈速度(800 MHz - GHz)的串列通信。由於高時脈速度的特性，高速串 列通信的硬體測試通常須要昂貴的量測儀器，不但測試成本太高，所須的測試時間也往 往太長而不符合經濟效益。 鑑於各種多媒體及網路應用對資料傳輸頻寬要求不斷增加，高速串列通信傳輸必將 成為下一代個人電腦或未來家庭娛樂中心的標準。發展高速串列通信標準的硬體測試技 術，將可提昇台灣未來資訊、娛樂電子產品的競爭力。 本計劃的目的在於發展高速串列通信傳輸媒介(transmission media)的測試技術。 初期將以Serial ATA (SATA)為起點，研發能降低測試時間及量測儀器性能需求的測試 技術，並將此技術轉移給合作廠商，中期則將推廣此技術至其它串列通信標準，未來則 希望將此技術運用於SoC內部高速資料傳送機制的測試。研究項目包括：(1) SATA cable 的模型建立，(2) SATA cable 結構性錯誤(structural defect)對性能影響的分析，(3) 性能導向的SATA cable結構性錯誤(structural defect)測試方法。Due to the limitation of clock skew, parallel communication has reached the bottleneck in terms of data transmission. As a result, parallel communication is gradually being replaced by high-speed serial communication. Take PC peripheral connection for example, newly established standards like USB 2.0, Firewire (IEEE 1394), and Serial ATA, are all high-speed serial communication standards ranging from 800 MHz to a few GHz. Due to the high clock rate, testing of the high-speed serial communication hardware often requires pricy test equipment and long test time, which is not efficient in a manufacturing testing environment. As the demand of multimedia and networking applications on data bandwidth multiplies, high-speed serial communication will become the mainstream for next-generation PCs and future home entertainment centers. Developing high-speed serial link testing techniques will certainly strengthen the competitive capacity of Taiwan’s industry in future electronics and entertainment products. The objective of this project is to develop testing techniques for high-speed serial communication data transmission media. We will start from the serial ATA (SATA) cable, develop for it cost-effective manufacturing testing techniques, and transfer the results to the cooperating company. Then, we will apply the techniques to other serial communication standards. Finally, we will study the testing of on-chip high-speed serial links. The main research topics include (1) SATA cable fault modeling, (2) techniques for evaluating the functional fault coverage of defect-based test set, and (3) test set selection for SATA cable.application/pdf109220 bytesapplication/pdfzh-TW國立臺灣大學電子工程學研究所高速度串列通信類比電路測試high-speed serial communicationanalog testingserial ATAreporthttp://ntur.lib.ntu.edu.tw/bitstream/246246/29235/1/912622E002049CC3.pdf