VHDL-Based Design and Analysis of Defect Tolerant VLSI/WSI Array Architectures

Kuo, Sy-YenSy-YenKuoWang, KungKungWang2009-02-042018-07-062009-02-042018-07-061991-01http://ntur.lib.ntu.edu.tw//handle/246246/121703en-USVHDL-Based Design and Analysis of Defect Tolerant VLSI/WSI Array Architecturesconference paper