Lu YChen YYu SYAO-WEN CHANG2022-04-252022-04-25202102780070https://www.scopus.com/inward/record.uri?eid=2-s2.0-85112211705&doi=10.1109%2fTCAD.2021.3101145&partnerID=40&md5=08f7d5df3010b00d43085ff8e1dcd98fhttps://scholars.lib.ntu.edu.tw/handle/123456789/607523The wavelength-routed optical network-on-chip (WRONoC) is a promising solution for signal transmission in modern system-on-chip (SoC) designs. Previous works do not simultaneously handle all the following four main issues for WRONoCs: correlations between the topological structure and physical layout, trade-offs between the maximum insertion loss and the number of wavelengths, runtime scalability of wavelength assignment scheme, and a fully automated flow to generate predictable designs. As a result, their insertion loss estimation is inaccurate, their wavelength assignment is inefficient, and thus only suboptimal results are obtained. To remedy these disadvantages, we present a fully automated topological structure and a physical layout co-design flow with improved wavelength assignment schemes to minimize the maximum insertion loss and the laser power simultaneously with a significant speedup. Experimental results show that our co-design flow significantly outperforms state-of-the-art works in the maximum insertion loss, laser power, and runtimes. IEEEHigh-speed optical techniquesInsertion lossLaser theoryLayoutOptical lossesOptical waveguidesPower lasersEconomic and social effectsFiber optic networksInsertion lossesIntegrated circuit layoutProgrammable logic controllersTopologyLoss estimationPredictable designSignal transmissionState of the artSystem on chip designTopological structureWavelength assignmentWavelength routed optical networksNetwork-on-chipEconomic and social effects; Fiber optic networks; Insertion losses; Integrated circuit layout; Programmable logic controllers; Topology; Loss estimation; Predictable design; Signal transmission; State of the art; System on chip design; Topological structure; Wavelength assignment; Wavelength routed optical networks; Network-on-chipjournal article10.1109/TCAD.2021.31011452-s2.0-85112211705