D.-L. ShenTAI-CHENG LEE2018-09-102018-09-102007-0200189200http://scholars.lib.ntu.edu.tw/handle/123456789/334012https://www.scopus.com/inward/record.uri?eid=2-s2.0-33847754746&doi=10.1109%2fJSSC.2006.889380&partnerID=40&md5=9339ce930c84d900f5aa3d4a48f20e3bA 6-bit 800-MS/s pipelined A/D converter (ADC) achieves SNDR and SFDR of 33.7 dB and 47.5 dB, respectively. Employing voltage-mode open-loop amplifiers in gain stages, global gain control techniques, and two-bank-interleaved architecture, the proposed pipelined A/D converter relaxes stringent design tradeoffs between speed and power. Fabricated in a 0.18-μm CMOS technology, the ADC consumes 105 mW from a 1.8-V power supply while the active area is only 0.5 mm2. © 2007 IEEE.Analog-digital conversion; CMOS analog integrated circuits; Gain controlTwo-bank-interleaved architecture; Voltage-mode open-loop amplifiers; CMOS integrated circuits; Electric potential; Gain control; Power amplifiers; Analog to digital conversionjournal article10.1109/jssc.2006.8893802-s2.0-33847754746WOS:000243915300002