Lu, D.-R.D.-R.LuHsu, Y.-C.Y.-C.HsuKao, J.-C.J.-C.KaoKuo, J.-J.J.-J.KuoNiu, D.-C.D.-C.NiuKUN-YOU LIN2018-09-102018-09-102012http://www.scopus.com/inward/record.url?eid=2-s2.0-84866788209&partnerID=MN8TOARShttp://scholars.lib.ntu.edu.tw/handle/123456789/372339In this paper, a high-gain and wideband low-noise amplifier using 65-nm CMOS process is proposed. A four-stage cascode configuration is adopted to achieve the high gain and wideband performance. With 24-mA dc current and 2-V supply voltage, the LNA not only provides gain higher than 20 dB from 75.5 GHz to 120.5 GHz, but also has a measured noise figure between 6 and 8.3 dB from 87 to 100 GHz. The output 1-dB compression power (OP 1dB) is 3 dBm at 110 GHz, and the chip size is 0.55 × 0.45 mm 2.CMOSLow noise amplifierMMICW-band[SDGs]SDG7conference paper10.1109/MWSYM.2012.62594812-s2.0-84866788209