2020-08-012024-05-15https://scholars.lib.ntu.edu.tw/handle/123456789/666353摘要：為了實現更自動與人性化的環境，智慧終端裝置越來越廣泛地被使用在攸關生命安 全及重要任務的應用上(如:汽車電子與航空電子)。為了提供使用上的彈性，這 些終端裝置基本上都使用處理器核心執行設定的工作程序並提供運算能力。與消費 性電子不同，這些裝置經常需要在嚴峻的操作環境下使用超過十年，而在其使用期 限內一旦發生錯誤，往往會造成嚴重的生命財產損失。這需要遠超過消費性電子產 品的可靠度。對IC量產測試而言，燒機(burn-in)是目前確保產品可靠度最好的 解決方案，卻有過於昂貴與效果隨著製程進步而效能變差的問題。適性測試被認為 有機會取代燒機。然而目前仍無法將測試脫逃(test escape)降到可接受的層度 ，尚無法完全取代燒機。 以軟體為基礎的處理器核心自我測試技術(Software-Based Self-Test — SBST)是一個可以與現有量產測試技術互補，進一步提升處理器核心可靠度的技 術。與以掃描鍊實施的量產測試技術相比，SBST是在處理器核心的正常工作模式 下執行，因此可以在系統生命週期間視需要執行，提早發現系統未被發現或由老化 造成的缺陷所導致的錯誤，接著執行系統預定的錯誤處理程序。 本計畫延續目前正在執行的一百零八年度計畫，繼續發展SBST技術，以提升處理 器核心的可靠度。計畫重點主要為:(1)提升自我測試程式產生過程的自動化程 度，與(2)降低對處理器核心設計細節的需求，目標是只需要指令及架構 (Instruction Set Architecture — ISA)與程式設計者可視的暫存器 (programmable visible registers)。<br> Abstract: To realize a more user-friendly and autonomous environment, smart edge devices are more and more commonly used in mission-critical applications, e.g., automotive electronics and avionics. To provide flexible services, these terminal devices rely on processor cores to execute the defined protocols and provide adequate computation powers. Compared to commercial electronics, these mission-critical devices are often required to operate in harsh environment for more than ten years. After deployment, failure during their designated lifetime may lead to severe loss of property and even lives. During IC manufacturing testing, the most effective approach to ensure product reliability is burn-in; however, burn-in is expensive and its effectives keeps decreasing as the IC fabrication technology advances. Attempts have been made to replace burn-in with adaptive test. However, the latter still suffers test escape and cannot completely replace burn-in. Software-based self-test can be utilized to further improve processor core reliability, and is an ideal complement to current manufacturing testing practices. Compared to full-scan based manufacturing testing techniques, SBST is executed in processor’s functional mode. Thus, it can be executed on demand during the processor’s life span. Once the process is found faulty, the system will execute predefined fault-handling procedures. This proposal is a continuing project of an ongoing SY108 MOST project on developing SBST techniques to enhance processor core reliability. This project will focus on (1) enhancing the level of automation, and (2) reducing the need of design knowledge to the level of ISA (instruction set architecture) and programmable visible registers.處理器以軟體實現的自我測試在線測試可靠度processorsoftware-based self-teston-line testingreliability