吳安宇臺灣大學：電子工程學研究所汪威Wang, WeiWeiWang2007-11-272018-07-102007-11-272018-07-102005http://ntur.lib.ntu.edu.tw//handle/246246/57629以鎖相迴路為基礎的時脈產生器，在時脈資料回復電路當中被廣泛的使用。振盪器決定鎖相迴路電路的操作頻率，為了符合更進階的應用，本論文提出一個適用於全數位式鎖相迴路的高速數位控制震盪器架構。提出的高速振盪器操作頻率介於140MHz至1040MHz，振盪器核心面積為345um*56um。此外，針對面積成本為考量的鎖相迴路應用，本論文也提出一個低成本的數位振盪器架構，讓控制單元複雜度大幅的降低。高速和彽成本的數位振盪器架構皆以UMC18 1P6M技術進行實作驗證，振盪器解析度皆可達到20ps。 時脈另一個重要的特性，脈寬，脈寬調整迴路在目前高速的需用裡逐漸的受到重視。在訊號互相干擾的系統晶片裡，類比被動元件容易亦容易受到溫度，串音，電容洩漏的影響。因此，在此論文中，我們提出一個全數位式脈寬調整迴路，適用於未來系統晶片的應用。全數位式脈寬調整迴路以UMC18 1P6M技術進行實現，配合五個脈寬放大級電路與五個脈寬衰減級電路，提出的脈寬調整迴路可操作在250MHz至1000MHz，電路面積為220um*180um。脈寬解析度達30ps。在全數位鎖相迴路和全數位式脈寬調整迴路交互工作中，時脈訊號將有抗雜訊、高速及可調脈寬的特性。The Phase-Locked Loop (PLL) is a widely used circuit for clock generator as system clock or Clock Data Recovery (CDR). A high-Speed architecture of Digitally-Controlled Oscillator (DCO) for All-Digital Phase-Locked Loop (ADPLL) is proposed for advanced specifications. The high-speed DCO is designed to operate from 140MHz to 1040MHz. The DCO core area is 345 um ´ 56 um. In addition, an area-efficient architecture is also introduced for low-cost applications. The hardware controller complexity can be reduced significantly. Prototype chips are both implemented with UMC 1P6M CMOS technology. The resolutions of both high-speed and area-efficient architectures are both achieved to 20ps. The Pulse-Width-Controlled Loop (PWCL) is adopted to meet the demand for pulse-width-specific and high-speed CMOS application today. In the noisy SOC environment, analog components are easily influence by temperature, crosstalk and leakage capacitance voltage. We develop All-digital Pulse Width Control Loop (ADPWCL) architecture for future SOC applications. A prototype ADPWCL design is realized in UMC 0.18 1P6M process. With 5 pulse amplifier stage and 5 pulse shrinker stage, the functions of ADPWCL can be performed from 250 MHz to 1 GHz. The ADPWCL core area is 220 um ´ 180 um. Pulse width acquisition step is about 30ps.With the cooperation of ADPLL and ADPWCL, the on-chip clock has the characteristics of noise-insensitive, high-speed, and pulse-width-programmable.Chapter 1 Introduction 1 1.1 Motivation and Goal 2 1.2 Thesis outline 5 Chapter 2 Overview of Phase-Lock Loop Circuits 7 2.1 Linear Phase-Lock Loop 7 2.2 Digital Phase-Lock Loop 8 2.3 All-Digital Phase-Lock Loop 9 Chapter 3 DCO Designs 11 3.1 Standard-cell-based DCO design 12 3.2 High-speed FTU 16 3.3 Area-efficient DCO Design 18 3.4 Phase/Frequency Detector 20 3.5 Simulations of high-speed DCO 21 3.6 Simulations of ADPLL 23 Chapter 4 Overview of Pulse-Width Control Loop 27 4.1 Pseudo-Inverter-Based PWCL [12] 28 4.2 AND-Gate-Based PWCL [10] 29 4.3 All-Digital PWCL 30 Chapter 5 All-digital PWCL Architecture 33 5.1 Digital Pulse Width Modulator (DPWM) 34 5.2 Digital Pulse Width Converter (DPWC) 35 5.3 Simulation of Digital Pulse Width Modulator 39 5.4 Simulation of DPWC Design 41 5.5 Simulation of proposed PWCL 41 Chapter 6 Chip Implementations 46 6.1 On-chip Clock Generator 46 6.2 All-Digital PWCL for High-Speed On-Chip Communication System 47 Chapter 7 Conclusions 54 Reference 551271432 bytesapplication/pdfen-US全數位式鎖相迴路全數位式脈寬調整迴路ADPLLADPWCLthesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/57629/1/ntu-94-R92943034-1.pdf