臺灣大學: 電子工程學研究所汪重光尤乙龍Yu, Yi-LongYi-LongYu2013-04-102018-07-102013-04-102018-07-102012http://ntur.lib.ntu.edu.tw//handle/246246/256715本論文致力研究於適合生醫應用，有效利用能量之類比數位轉換器，並且提出製作於一百八十奈米製程之互補式金屬氧化半導體的逼近暫取器型類比數位轉換器使用主動-被動數位類比轉換器技巧。而量測之結果可以證實此技巧確實達到將低能量消耗的效果。 主動-被動數位類比轉換器技巧是使用一個附增的主動數位類比轉換器但只增加百分之五的面積，如此可以有效的防止因為在傳統型電容陣列中，重複的充電與放電在相同電容中所造成的能量浪費尤其是在較大的位元中的浪費。而運作的方式共分為四個步驟：取樣、主動數位類比轉換器工作、位元傳送和被動數位類比轉換器工作。而主動數位類比轉換器的最佳化位元數目與能量消耗都有被分析與經過模擬的驗證。 測試版適合生技應用的使用主動-被動數位類比轉換器逼近暫取器型類比數位轉換器達到十位元的解析度工作於五十萬赫茲的取樣頻率使用一伏的供給電壓。在符合不匹配現象下電容陣列中減少的能量比例是百分之九十三相較於傳統型的電容陣列。核心面積是零點一五毫米平方並且與傳統式的電容陣列相較下也減少了百分之七十五的面積。再量測的結果上達到了訊雜扭曲比五十九點二分貝，相當於九點六位元的等效位元數，整體功率消耗也因主動-被動數位類比轉換器技巧而有顯著的減少，總消耗功率為二十八微瓦質量指標為七十七費焦耳每轉換步驟。整體而言本論文提供一減少電容陣列能量消耗的技巧，並且由實做的晶片得到此技巧功能的驗證。This thesis researches an energy-efficient analog to digital converter (ADC) for bio-medical applications, and proposes a master-slave digital to analog converter (M-S DAC) technique implemented in a successive approximation register analog (SAR) ADC chip fabricated in 180nm CMOS. The function of energy-reduction is demonstrated by the measurements of the chip. The M-S DAC technique using an additional master DAC (MDAC) with extra area of 5% in capacitor array can prevent energy from waste in vain, which is caused by the repeatedly charge and discharge in the same capacitor of conventional capacitor array, particularly in larger bits. The sequences of M-S DAC are sampling, MDAC cycling, bit transferring, slave DAC (SDAC) cycling. The optimum number of bits and energy dis-sipation in the capacitor array is analyzed and identified by the simulation and meas-urements. The prototype SAR ADC using the M-S DAC has the resolution of 10-bit, sam-pling rate at 500KS per second with supply voltage of 1V which is adopted by bio-applications in common. The reduction ratio of energy dissipation in capacitor array is 93% in this work within the mismatch constraint and the core area is 0.15 mm2 with the area-reduction of 75% in capacitor array compared with conventional array. This prototype achieves the signal-to-noise-and-distortion-ratio of 59.2dB in equivalent to effective number of bits of 9.6-bit in measurement. The power consumption significantly reduces by M-S DAC technique. The total power is 28μW and it reaches the FoM 77fJ/Conversion-step. Conclusively, this thesis provides a technique for capacitor array to reduce energy dissipation, and demonstrated the function of the technique by a fabri-cated chip.140 bytestext/htmlen-US生醫應用低功率逐次逼近暫取器型類比數位轉換器主動-被動數位類比轉換器不匹配電容陣列bio-applicationlow powerlow voltageSAR ADCenergy-efficientM-S DACmismatched capacitor arraythesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/256715/1/index.html