黃鐘揚臺灣大學:電機工程學研究所蔡曉傑Cai, Siao-JieSiao-JieCai2010-07-012018-07-062010-07-012018-07-062009U0001-1508200921440500http://ntur.lib.ntu.edu.tw//handle/246246/188130由於SystemC是一個越來越普遍用來處理日益複雜的現代系統層級設計的塑模語言，在SystemC 設計上進行快速，準確地模擬，和執行牢靠的功能驗證的工具已成為整個設計流程中最重要的部分。由於傳統的編譯代碼模擬器是將一個SystemC設計編譯到低階可執行程式，它們只能進行模擬驗證。因此，當設計存在不單純的錯誤，例如死鎖情況，幾乎是不可能的去進一步分析設計的功能性以找出錯誤原因。此論文中，我們針對SystemC設計提出了一個延伸斐氏網路模型。此外，基於這個模型，我們還實作了一個SystemC的模擬器。由於擁有一個SystemC設計的內部表示以及對於模擬時排程的控制性，我們將可以對SystemC設計進行死鎖檢查。我們提出的演算法首先分析了SystemC設計中並行程序彼此之間事件同步的相依性。同時，我們將此相依性透過一個圖形化的資料結構呈現給設計者，以幫助他們瞭解死鎖產生的原因。透過幾個有效的例子，我們將證明所提出的模型和死鎖檢查的正確性。 外，我們所提出的延伸斐氏網路模型也可以作為SystemC設計的正規表示。這為未來對於應用正規驗證技術於SystemC設計上的研究開創相當大的可能性。As SystemC is becoming the prevailing modeling language to handle the increasing complexity of the modern system-level designs, tools to conduct fast and accurate simulation and perform solid functional verification on SystemC designs have become the most critical component in the design flow. Since conventional compiled code simulators compile the SystemC designs into low-level executable programs, they can only perform simulation-based validation. Therefore, it is virtually impossible to further analyze the design functionality for the non-trivial design errors such as dead-lock condition. n this thesis, we proposed an extended Petri-Net model for SystemC designs. We also implemented a SystemC simulator based on this model. With the internal representation of the SystemC designs and the controllability on the simulation scheduling, we are able to perform the deadlock checks of the SystemC designs. Our proposed algorithm first analyzes the dependencies of the event synchronization for the concurrent processes in the SystemC design. And a graph data structure is then presented to help designers to figure out the causes of the deadlock. We will demonstrate the correctness of the proposed model and the deadlock checking through several working examples. urthermore, the proposed extended Petri-Net model can also act as a formal representation of a SystemC design. This brings up a lot of possibilities for the research with formal verification techniques in the future.口試委員會審定書 #謝 i要 iiBSTRACT iiiABLE OF CONTENTS ivIST OF FIGURES viiIST OF TABLES ixIST OF ALGORITHMS xhapter 1 Introduction 1.1 Introduction to Electronic System Level Designs 1.2 Objectives of the Thesis 2.3 Previous Works 3.4 Organization of the Thesis 3hapter 2 Preliminaries 5.1 SystemC Overview 5.1.1 SystemC Components 5.1.2 SystemC Simulation Kernel 8.2 Event in SystemC 10.2.1 Static and Dynamic Sensitivity 10.2.2 Event Notification 12.3 Deadlock in SystemC 12.4 Basic Concepts of Petri Net 14.4.1 Basic Definitions 15.4.2 Executions Rules 17hapter 3 Proposed Extended Petri Net Model of SystemC Designs 20.1 Review of the Previous Extended Petri Net Model 20.2 Proposed Extended Petri Net Model 20.3 Modeling of C++ Construct 22.3.1 Variables 23.3.2 Expressions Statements 23.3.3 Conditional Expressions 26.3.4 Control Flow Statements 27.4 Modeling of SystemC Construct 29.4.1 Process 29.4.2 Port and Signal 30.4.3 Wait Statement 32.4.4 Event Notification 34hapter 4 SystemC Simulation Using Proposed Extended Petri Net Model 36. Overview of the Extended Petri Net SystemC Scheduler 36.2 Simulation Algorithm for Extended Petri Net Model 37.3 SystemC Simulation Kernel on Extended Petri Net Model 37.3.1 Initialization Phase 38.3.2 Evaluation Phase 38.3.3 Update Phase 39.3.4 Time Notification Phase 39hapter 5 Petri Net Based Static Property Checker 40.1 Overview of Static Property Checker on Petri Net Model 40.2 Dynamic Synchronization Dependency Graph 41.3 Proposed Predictive Synchronization Dependency Graph 42.4 Modeling of Deadlock Checking 45.5 Structural Checking of PSDG 47.6 Simulation Based Deadlock Checking 53.6.1 Heuristic Watch Criteria 55.7 Comparison with Previous Works 57hapter 6 Experimental Results 59.1 Test Cases Description 59.2 SystemC to Extended Petri Net Translation 60.3 Deadlock Checking 64.4 Profiling Result of Execution Time 67.5 Comparision with OSCI SystemC Simulator 68hapter 7 Conclusion and Future Work 70EFERENCE 721199986 bytesapplication/pdfen-USSystemC死鎖模擬確認電子系統層級deadlocksimulation validationelectronic system levelthesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/188130/1/ntu-98-R96921034-1.pdf