電機資訊學院: 電子工程學研究所指導教授: 林浩雄沈威廷Shen, Wei-TingWei-TingShen2017-03-062018-07-102017-03-062018-07-102016http://ntur.lib.ntu.edu.tw//handle/246246/276701本論文利用氧化層磊晶系統（Oxide MBE）分別製作氧化釔（Y_2 O_3）與釔參雜氧化鍺（Y - GeO_2）在鍺（Ge）基板上並鍍上金屬閘極作成金氧半電容元件（Metal – oxide – semiconductor capacitor, MOSCap）並分析其特性。主要目的為判斷鍺基板與高介電係數材料（High – k materials）間是否需存在一夾層（Interfacial layer）當作緩衝層（Buffer layer）。此外，將釔參雜入氧化鍺內有助於增強其化學鍵結進而改善元件特性，包含介電係數之提升與漏電流之下降等 ……。 透過導入金屬後退火（Post – metallization annealing, PMA）製程有助於電容元件特性之改善，包含邊緣缺陷（Border traps）及界面缺陷密度（Interface – trap density, D_it）之降低。這些缺陷之減少反應在電容特性上的現象即為磁滯（Hysteresis）的下降與頻散（Frequency dispersion）的改善。除此之外，我們發現 250 ℃ 的退火條件會使漏電流降低，這是因為合成氣體（Forming gas）中之氫氣有效地修補氧化層中之斷鍵（Dangling bonds）並使之變得更為緻密所致。 利用變頻電容量測搭配高低頻電容法（High – low – frequency capacitance method）之計算，元件在室溫下之最小界面缺陷密度為 9.099 × 〖10〗^11 eV^(-1) cm^(-2)。最後，透過不同電流（Emission current）製程條件下所製作之元件其界面缺陷密度的比較可知，為了得到較好之半導體氧化層接面（界面缺陷密度較低），鍺基板與高介電係數材料之間需要有一層釔參雜氧化鍺來當作緩衝層（Buffer layer）。In the dissertation, the oxide MBE system was harnessed to synthesize both yttrium oxide（Y_2 O_3）and yttrium – doped germanium oxide（Y - GeO_2）on germanium substrate. Then, the metal – oxide – semiconductor capacitor, MOSCap, devices were fabricated after metal was deposited on the semiconductor – oxide samples by utilizing the e – gun evaporator. The primary purpose was to determine whether the interfacial layer was necessary between Ge substrates and high – k materials as a buffer layer in Ge – based MOSCap devices. Additionally, due to the instable properties of GeO_2, yttrium atoms were doped into GeO_2 to strengthen the chemical bonding and ameliorate the overall performances of MOSCap devices, including higher dielectric constant（k）and lower leakage current density, etc. Using post – metallization annealing, PMA, was beneficial to improve the electrical characteristics in numerous aspects. Both border traps and interface – trap density（D_it）were observed to be lower after going through the process of PMA. The former could be clarified by the reduction of hysteresis and frequency dispersion in C – V measurement, the latter was confirmed by the calculation of high – low – frequency capacitance method. Furthermore, leakage current density of the devices was found to be lower in the PMA condition of 250 ℃. The explanation of the phenomenon was the repair of dangling bonds in oxide by hydrogen atoms in forming gas. In room temperature, the minimum value of interface – trap density of devices was 9.099 × 〖10〗^11 eV^(-1) cm^(-2) by utilizing the high – low – frequency capacitance method. At last, by comparing the interface – trap density of devices fabricated by a series of emission current, we concluded that the interfacial layer was needed between Ge substrates and high – k materials as a buffer layer due to lower D_it, indicating better interface quality than direct contact of Ge substrates and high – k materials.2564391 bytesapplication/pdf論文公開時間: 2019/8/24論文使用權限: 同意有償授權(權利金給回饋學校)鍺氧化釔釔參雜氧化鍺氧化層磊晶金氧半電容元件界面缺陷密度GermaniumYttrium oxideYttrium – doped germanium oxideOxide MBEMetal – oxide – semiconductor capacitanceInterface – trap densitythesis10.6342/NTU201602217http://ntur.lib.ntu.edu.tw/bitstream/246246/276701/1/ntu-105-R03943053-1.pdf