Wu S.-SChen H.-HLIANG-GEE CHEN2022-04-252022-04-25202110518215https://www.scopus.com/inward/record.uri?eid=2-s2.0-85114606776&doi=10.1109%2fTCSVT.2020.3040774&partnerID=40&md5=b6b840b27403a6f6122ebad37d30a7fehttps://scholars.lib.ntu.edu.tw/handle/123456789/607242Belief propagation (BP)-based stereo matching has popular owing to its regularity and ability to yield promising results. Some commonly observed hardware-implementation challenges pertaining to the use of this algorithm are large memory requirements and trade-offs between speed and chip area, along with an increasing disparity range. The paper presents a hardware- and memory-efficient architecture for building a BP-based disparity estimation system capable of overcoming issues associated with large disparity ranges. The proposed architecture is memory-efficient owing to the regularity of its underlying algorithm. In addition, the improved hardware efficiency can be attributed to processing element modifications to demonstrate shareable characteristics. Results obtained in this study reveal a 67.8% reduction in required memory corresponding to a time-area term complexity of O(L(logL)^{2}) , where L denotes the disparity range. This result is in stark contrast to the O(L^{2}logL) and O(L^{2}) complexities observed in extant studies. Compared to state-of-the-art implementations, the proposed architecture offers an 86.2% gate count reduction for message update units at a disparity range of 512. These results confirm the proposed architecture's suitability for use in large disparity scenarios. ? 1991-2012 IEEE.Belief propagation media (BP-M)disparity estimationsmemory-efficient architecturestereo matchingtile-based belief propagationVLSI circuit designEconomic and social effectsBelief propagationDisparity estimationsHardware efficiencyHardware implementationsMemory requirementsProcessing elementsProposed architecturesState of the artMemory architecturejournal article10.1109/TCSVT.2020.30407742-s2.0-85114606776