電機資訊學院: 資訊工程學研究所指導教授: 楊佳玲王少甫Wang, Shao-FuShao-FuWang2017-03-032018-07-052017-03-032018-07-052015http://ntur.lib.ntu.edu.tw//handle/246246/275542近年來，非揮發性記憶體技術的進步提供了新一代記憶體系統設計的基礎。由於非揮發性記憶體具備介於傳統記憶體及硬碟的混合特性，如較高的密度，可位元組定址，以及非揮發性等特性，使系統結構設計師重新思考傳統的記憶體階層架構。透過將非揮發性記憶體作為主記憶體，程式設計師可以直接將非揮發性資料結構儲存於主記憶體，並以 ld/st 指令直接存取。為預防突發的系統崩潰及斷電，我們會透過預寫式日誌保證非揮發性資料結構的一致性。由於現代的記憶體控制器為了增加記憶體庫平行度，會亂序排程記憶體寫入順序，因此，許多文獻使用 Persist Barrier 保證正確的寫入次序。然而，我們觀察到 Persist Barrier 會造成多餘的寫入順序限制，並且造成記憶體庫平行度下降，使得系統效能降低。在本論文中，我們提出 Semantics-aware Memory Scheduler。透過使用一新軟硬體介面，應用程式可將寫入日誌的語意轉送至記憶體控制器，使Semantics-aware Memory Scheduler 能夠分辨記憶體請求是寫入實際資料或寫入日誌，並除去多餘的寫入順序限制。透過允許更多的同時寫入，記憶體控制器可以最大化記憶體庫平行度並提供更多效能。全系統模擬實驗的結果顯示，Semantics-aware Memory Scheduler 可改善最多 2.89 倍以及平均 2.13 倍的寫入效能。The maturity of emerging non-volatile memory (NVM) technologies presents promising next-generation memory system design. Because of its mixed performance characteristics between DRAM and persistent store, e.g., high density, byte-addressability, and non-volatility, architects rethink the design of traditional memory hierarchy. With NVM as main memory, programmer can place non-volatile data structures on main memory and directly access them by ld/st instructions. Non-volatile data structures demand consistency and atomicity guarantees in case of sudden system crash. To guarantee consistency and atomicity, some forms of write-ahead logging (WAL) semantics are needed. Because modern memory controller reorders writes to exploit bank-level parallelism, persist barrier is adopted by many existing works to guarantee the order between writes. However, we observe that persist barriers introduce unnecessary write ordering constraints and hurt the system performance by restricting memory controller from exploiting bank-level parallelism. In this thesis, we propose Semantics-aware Memory Scheduler. By using a new software/hardware interface to transfer knowledge of application''s logging semantics to memory controller, Semantics-aware Memory Scheduler eliminates unnecessary write ordering constraints by differentiating between log writes and target data writes. Through allowing more concurrent memory writes, memory controller can provide more performance by maximizing bank-level parallelism. Experimental results of full-system simulation show that Semantics-aware Memory Scheduler can improve throughput by up to 2.89x (2.13x on average).1251400 bytesapplication/pdf論文公開時間: 2020/8/21論文使用權限: 同意有償授權(權利金給回饋本人)非揮發性記憶體儲存類別記憶體相變化記憶體記憶體排程器記憶體管理資料一致性Non-volatile MemoryStorage Class MemoryPhase-change MemoryMemory SchedulerMemory ManagementConsistencythesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/275542/1/ntu-104-R02922070-1.pdf