陳少傑臺灣大學：電子工程學研究所陳建村Chen, Chien-TsunChien-TsunChen2007-11-272018-07-102007-11-272018-07-102004http://ntur.lib.ntu.edu.tw//handle/246246/57457隨著通訊技術的成長以及區域網路的進步,資料傳輸的速率要求和通訊的品質變得愈來愈重要了。在數位通訊系統中有幾個重要因素影響著通訊速度及品質。其中一項重要的影響因素就是多重路徑效應所引起的選擇性衰落及碼間干擾。為了解決碼間干擾效應，一個有效且夠強大的選擇就是等化器。為求架構的精簡及線性穩定上的需求，我們使用最小方均根演算法去實現這等化器。由於收斂速度的要求，我們使用決策回授等化器架構來做設計。其中有四個主要部分，包含兩個有限脈衝濾波器即前饋式及回授式濾波器、係數調整器及決策器。此可適性回授等化器只用了兩個三階的有限脈衝濾波器。它可以4us裡訓練訊號至正確。在這次設計我們使用了台灣積體電路公司0.35 2P4M製程技術。此可適性回授等化器在3.3V的供應電壓下消耗必v為54.99mW。With the growth of the communication technology and Local Area Network (LAN), communication quality has become more and more important. In digital communication systems, there are many factors that affect the communication quality. One of the main factor decreasing system performances is inter-symbol interference (ISI) which come from the multi-path effect. To eliminate the ISI problem, we use an equalizer to solve this problem. In order to achieve linearity and stability, we use a Least-Mean-Square (LMS) algorithm to implement the equalizer. And due to the speed issue and convergence of recovery, we use a decision feedback equalizer architecture for this design. It consists of four main parts: two FIR filters, a Feed-Forward filter and a Feed-Back filter, and a block of update coefficients, and a slicer. We implement this decision feedback equalizer (DFE) by using two 3-tap FIR filters. It can also train the signal to correct in 44 chips (about 4μs). In this design, we use the TSMC CMOS 0.35μm 2P4M process technology. The DFE consumes 53.99 mW with a 3.3V supply voltage.TABLE OF CONTENTS ABSTRACT …………………………………………………………………… i LIST OF FIGURES …………………………………………………….....… v LIST OF TABLES …………………………………………………………..… ix CHAPTER 1. INTRODUCTION ……………………………………………… 1 1.1 Background ….………………..………………………………… 1 1.2 Organization of This Thesis .……………………………….…… 1 CHAPTER 2. OVERVIEW OF HIGH-SPEED WIRELESS LAN ……….. 3 2.1 A Brief History of Wireless Communication Systems ….……... 4 2.2 Digital Communication System ……………………………….. 5 2.3 Introduction to the IEEE 802.11b ……………………………… 6 2.4 Direct Spread Spectrum Technology and Modulation ………… 8 2.5 Multi-Path Modeling ……………………………………………… 12 2.5.1 IEEE 802.11 Channel Model ………………………… 12 2.5.2 Saleh and Valenzuela Channel Model ……........…… 13 CHAPTER 3. BASEBAND PROCESSOR ……………………………… 15 3.1 Introduction to Transmitter Architecture ………………………… 17 3.2 Modulation Technology ………………………………………… 19 3.2.1 Differential Binary Phase Shift Keying ……………… 19 3.2.2 Differential Quadrature Phase Shift Keying ………… 20 3.2.3 Complementary Coke Keying ………………………… 21 3.3 Introduction of Receiver Architecture ………………………… 24 CHAPTER 4. DECISION FEEDBACK EQUALIZER BASED ON LMS ALGORITHM …………………………………………..……………… 31 4.1 Algorithms for Adaptive Filter …………………………………… 32 4.2 Least-Mean-Square Algorithm ……………………………… 33 4.3 Introduction of Digital Filter …………………………………… 36 4.4 Adaptive Decision Feedback Equalizer ………………………… 40 4.4.1 Introduction to Adaptive Filter ………………………… 40 4.4.2 Structure of Decision Feedback Equalizer ……………… 43 CHAPTER 5. SIMULATION AND IMPLEMENTATION OF DFE ………… 47 5.1 Simulation of DFE ……………………………………………… 48 5.2 Implementation of DFE ………………………………………… 53 CHAPTER 6. CONCLUSION ……………………………………………… 57985068 bytesapplication/pdfen-US可適應性決策回授等化器最小均方法等化器adaptive decision feeback equalizerequalizerLMSthesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/57457/1/ntu-93-R91943079-1.pdf