盧信嘉臺灣大學：電子工程學研究所趙子威Chao, Tzu-WeiTzu-WeiChao2007-11-272018-07-102007-11-272018-07-102006http://ntur.lib.ntu.edu.tw//handle/246246/57719這篇論文包含了三個研究主題，第一個研究主題為毫米波頻帶之覆晶轉接特性之量測，第二個為低溫共燒陶瓷中效能改善之電感，最後是在多層結構中較高製程變異容忍度的電容與耦合電感之設計。 由資料研讀及模擬結果可知傳統覆晶的轉接特性，並且關於其的窄、寬頻的改善方法也一並討論及模擬。然後我們使用兩種量測方法來量測覆晶的特性，一種是背對背的覆晶量測方法，另一種則是埠數降低量測法。在此，設計並且模擬一個使用於埠數降低量測法中的互補場效電晶體可程式負載之電路。 為了設計一個高效能電感，我們探討且分析了電感內的物理現象及電感幾何結構對於電感效能的影響。然後我們設計了單層螺旋型、多層螺旋型、螺旋狀及立體螺線管的電感，並且比較其電感值、品質因素及自振頻率。為了改善電感效能，我們設計了部分接地層掏空及圖樣接地層結構之電感。最後設計了應用於差動電路的中心外接之對稱電感，以增加其的電路對稱特性。全部的電感設計都是在低溫共燒陶瓷的製程中完成。 由於現今多層結構中製程仍存在著相當的變異，使得層與層之間無法完全對齊而造成其中的電路特性偏移。為了解決此問題，我們提出了較高製程變異容忍度的電容及耦合電感之設計。經由較高製程變異容忍度的元件設計出傳輸零點電路及帶通濾波器以驗證其對電路系統的效能改善。There are three topics in this thesis. The first topic is the flip-chip transition measurement up to millimeter wave frequency. The second is the design of performance improved inductors in the LTCC substrate. The last is the capacitor and coupled inductor with high process tolerance in the multilayer structure. The characteristics of the conventional flip-chip are studied and obtained by the simulation. Its narrowband and wideband improvements are simulated and presented. Then we propose two measurement methods to extract the property of the flip-chip up to millimeter wave frequency. One is back-to-back flip-chip measurement method and the other is PRM (port reduction method). The programmable termination in CMOS circuit is designed and simulated for PRM. To optimize the inductor design, the influence of the geometry on the inductor’s performance are introduced and analyzed. Then the spiral, multilayer, helical and solenoid inductors are designed and its performance on inductance, quality factor and self resonant frequency are compared. The spiral inductors with patterned or hollow ground are analyzed and designed to improve its performance. Finally, the center tapped inductors are designed for differential circuit with better symmetry property. All of inductors are designed in the LTCC substrate. The capacitor and coupled inductor with high process tolerance are proposed to withstand the misalignment between stacked layers due to process variation. The transmission zero circuit and bandpass filter implemented with these components are designed and simulated to test the performance of high process tolerance in the circuit level.Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Introduction to flip-chip technology 2 1.3 Introduction to LTCC technology 6 1.4 Overview 11 Chapter 2 Conventional flip-chip transition and its improvement 13 2.1 The property of conventional flip-chip transition 13 2.2 Narrowband improvement 19 2.2.1 Single resonance flip-chip transition 19 2.2.2 Transformer flip-chip transition 23 2.3 Wideband improvement flip-chip transition 27 2.3.1 Local compensation flip-chip transition 28 2.3.2 Inductive Compensation Flip-chip transition 30 2.4 Conclusion 37 Chapter 3 Flip-chip measurement methods 39 3.1 Two methods for flip-chip transition measurement 39 3.2 Back-to-back TRL flip-chip measurement method 40 3.3 PRM (port reduction method) for flip-chip transition measurement 41 3.3.1 PRM for reconstruction of the two-port scattering matrix using measurement only at one port 42 3.3.2 The design of programmable termination in IC 44 3.4 Conclusion 51 Chapter 4 Inductors in LTCC 53 4.1 The inductance of a spiral inductor 54 4.2 The loss mechanism of an inductor in LTCC 55 4.2.1 Eddy current 56 4.2.2 Metal loss 56 4.2.3 Substrate loss 57 4.3 The electrical model of an inductor in LTCC 59 4.3.1 Equivalent π model of an inductor 59 4.4 Quality factor definition 62 4.4.1 Qconv definition 62 4.4.2 The method for Qconv prediction 63 4.5 Influence of the geometry on the inductor’s performance 65 4.6 Performance of spiral, helical, multilayer and solenoid inductors 66 4.6.1 Spiral inductors 67 4.6.2 Multilayer inductor 69 4.6.3 Helical inductor 70 4.6.4 Solenoid inductor 71 4.6.5 Comparison of spiral, multilayer, helical and solenoid 73 4.7 The spiral inductors with patterned and hollow ground 74 4.8 The center tapped inductor 77 4.9 Conclusion 79 Chapter 5 Capacitor and coupled inductor with high process tolerance in LTCC...81 5.1 Straight line coupled inductors and its equivalent circuit 82 5.2 Coupled inductors with high process tolerance 84 5.3 Capacitors with high process tolerance 86 5.4 Transmission zero circuit implemented with high process tolerance components 87 5.5 Single bandpass filter implemented with high process tolerance components 91 5.6 Conclusion 95 Chapter 6 The measurement procedure and results 97 6.1 The measurement procedures for single-port circuits 98 6.2 The measurement procedures for differential-port circuits 99 6.2 The measurement procedures for flip-chip transitions 101 6.2.1 Back-to-back TRL flip-chip measurement method 101 6.2.2 PRM for flip-chip transition measurement 102 6.3 Measurement result of the transmission zero circuits………………………..103 Chapter 7 Conclusion 1072490259 bytesapplication/pdfen-USflip-chipLTCCPRMInductorsspiralmultilayerhelicalsolenoidpatterned groundhollow groundcenter tappedprocess tolerancemisalignmentcoupled inductor覆晶低溫共燒陶瓷埠數降低量測法電感螺旋多層螺旋狀立體螺旋圖樣接地層部分接地層掏空中心外接製程變異容忍度偏移耦合電感thesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/57719/1/ntu-95-R93943070-1.pdf