Dept. of Electr. Eng., National Taiwan Univ.Chang, Hao-ChiehHao-ChiehChangYang, Zhong-LanZhong-LanYangLian, Chung-JrChung-JrLianLIANG-GEE CHEN2018-09-102018-09-102001https://www.scopus.com/inward/record.uri?eid=2-s2.0-0035023720&doi=10.1109%2fISCAS.2001.921040&partnerID=40&md5=ba4ff37272c4614e20daf3afb45baa31http://scholars.lib.ntu.edu.tw/handle/123456789/292082This paper presents a hardware-efficient architecture of tree-depth scanning (TDS) and multiple-quantization (MQ) scheme for MPEC-4 still texture coding. By means of the novel architecture, the TDS can achieve its maximal throughput to area ratio and minimal external memory access with only one wavelet-tree size on-chip memory. Besides, MQ adopts the proposed POT (power of 2) quantization, which is proved to have very similar performance to generic (user-defined coefficients) scalar quantization, to achieve the most cost-effective hardware implementation. The prototyping chip has been implemented in a TSMC 0.35 /spl mu/m CMOS technology. This architecture can handle 30 4-CIF frames per second with 5 spatial layers and 3 SNR layers scalability at 100 MHz clock frequency. © 2001 IEEE.application/pdf424331 bytesapplication/pdfArchitecture designs; External memory access; Frames per seconds; Hardware implementations; Maximal throughput; Multiple quantizations; Novel architecture; Scalar quantization; CMOS integrated circuits; Forestry; Motion Picture Experts Group standards; Image compression; Microprocessor chips; Scanning; Signal to noise ratio; Software prototyping; Vector quantization; Hardware; Image coding; Multiple quantization (MQ); Tree depth scanning (TDS)conference paper10.1109/ISCAS.2001.9210402-s2.0-0035023720